EPM1270 i/o problem

[Altera_Forum]

I read a CS5532 when EPM1270 found a problem. I give an order of 5532, when the internal logic of concurrent write a command to the SCLK pin on the pin but occasionally did not wave. I count the internal logic of the output and found that the data actually sent me, just do not know why the pin did not respond. So I divided by the system clock connected to the SCLK pin when the pin output is also normal, no-no wave.

[Altera_Forum]

Sounds like a logic design error, e.g. timing related. Without knowing design details and exact observations, we can only guess about it.

[Altera_Forum]

module _ad_spi( 

input wire clk,//  input wire rst_n,  input wire _init_start,  input wire output_enable,  input wire output_flag,  input wire [7:0] _AD_indata,    output reg [23:0] _AD_outdata,  output reg _Get_Data_Flag_out,    output reg _AD_sclk,//SPI port  output reg _AD_sdo,  input wire _AD_sdi  ); reg [2:0] state; // statemachine state reg [5:0] transmit_count; //transmit count reg [23:0]_AD_data; //temp 24bits data reg _get_data_over; //get data over flag reg [7:0] treg; //transmit reg ///////////////////////////////////////////////////////////////////////////// always @(*)//out put data begin if(!rst_n) _AD_outdata <=0; else if(output_enable&&_get_data_over == 1) _AD_outdata <= _AD_data; end ///////////////////////////////////////////////////////////////////////////// always @(posedge clk or negedge rst_n)  if (~rst_n)  begin  state <= 3'b000; // idle  transmit_count <= 6'b000000;  treg <=# 1 8'h00;  _AD_sclk <= 1'b0;  _AD_sdo <= 0;  end  else  begin  _Get_Data_Flag_out <= 0;  case (state) //synopsys full_case parallel_case  3'b000: // idle state  begin  transmit_count <= 6'b000000; // set transfer counter  treg <= 8'h00; // load transfer register  _AD_sclk <= 1'b0; // set sck  _AD_sdo <= 1'b0;  if(output_flag )//&_init_start)  begin  treg <= _AD_indata;// load transfer register  transmit_count <= 6'h7; // set transfer counter  state <= 3'b001; // transfer data state  _Get_Data_Flag_out <= 1;  _AD_sdo <= _AD_indata[7];  end  else if (~_AD_sdi)// & ~_init_start)  begin  transmit_count <= 6'h28; // set transfer counter  state <= 3'b001; // transfer data state  _get_data_over <= 0;  end  end  3'b001: // clock-phase2, next data  begin  _AD_sclk <= ~_AD_sclk;  if(transmit_count == 6'h7)  state <= 3'b011; // send data state  else if(transmit_count == 6'h28)  state <= 3'b101; // recive data state  else   state <= 3'b000; // idle state  end  3'b011: //send data state  begin  if(~_AD_sclk)  begin  _AD_sdo <= treg;  transmit_count <= transmit_count -6'h1;  end  if (~|transmit_count)  begin  state <= 3'b000;  _AD_sclk <= 0;  _AD_sdo <= 0;  end   else   begin  state <= 3'b011;  _AD_sclk <= ~_AD_sclk;  end  end  3'b101: //recive data state  begin  if(_AD_sclk)  begin  if(transmit_count >7 && transmit_count < 32)  _AD_data <= _AD_sdi;  transmit_count <= transmit_count -6'h1;  end  _AD_sdo <= 0;    if (transmit_count == 0 || transmit_count >40)  begin  state <= 3'b000;  _AD_sclk <= 0;  if(transmit_count >40) _get_data_over <= 0;  else _get_data_over <= 1;  end   else   begin  state <= 3'b101;  _AD_sclk<= ~_AD_sclk;  _get_data_over <= 0;  end  end  default: state <= 3'b000;  endcase  end endmodule     This is my program, you help me see, what is the problem

[Altera_Forum]

I count the SCLK output is normal, and SCLK, and DOUT is simultaneously, or both did not