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Altera_Forum
Honored Contributor I
949 Views

Configuration Cyclone V 5CEBA9F23C8N

I Design Board With 5CEBA9F23C8N  

I choose AS Configuration for programming & EPCS128 

After Develop PCB I start to program my board  

 

STEP1- Compile My Design in quartus 16.1(SIMPLE LED ON FOR TESTING) 

STEP2-CONVERT .SOF FILE TO .POF (FOR ACTIVE SERIAL EPCS128) 

STEP3-PROGRAM EPCS128 VIA PROGRAMMING(I SELECT ACTIVE MODE) 

STEP4- SUCESSFULLY EPCS128 PROGRAM 

But my fpga didn’t program L 

So I check every pin realated to fpga and epcs128 for programming 

Every pin is work fine except nstatus and dclk 

Nstatus stay in low alltime & dclk didn’t have clock 

I think the fpga stay in POR but I didn’t find out reason 

Anyone knows whats reason? 

(I have experience for design fpga board with max10 but max10 have internal flash & this my first experience with epcs128)
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10 Replies
Altera_Forum
Honored Contributor I
94 Views

I presume you have also a JTAG interface in your design. Can program the FPGA through JTAG? 

If so, you can also check the AS flash connection through JTAG indirect programming. 

 

Once you understand the JTAG indirect programming feature, you'll realize that a dedicated AS programming interface for your board is pretty superfluous, everything can be achieved through JTAG.
Altera_Forum
Honored Contributor I
94 Views

unfortunately i dont have jtag interface i only use as mode  

:( 

i try to find out why i havnt dclk  

is it possible for my supply tramp?
Altera_Forum
Honored Contributor I
94 Views

 

--- Quote Start ---  

unfortunately i dont have jtag interface i only use as mode 

--- Quote End ---  

 

I guess this will be your first and last FPGA design without JTAG interface... 

 

Unfortunately the schematic pictures aren't readable due to bad quality, so we can't check the connections. In the part that's still readable it's unclear how your providing MSEL setting. 

 

It can be a lot like missing power supplies (POR not released), wrong MSEL, solder problems, wrong pinout. 

 

Complete & readable schematics may help, but not sure if we can do much for you from a distance.
Altera_Forum
Honored Contributor I
94 Views

After reviewing the better readable schematic you posted at Edaboard (why not here?) http://www.edaboard.com/thread363521.html, I realized that VCCBAT is floating. According to CV pin connection guidelines, this might hold the device in POR. 

 

 

--- Quote Start ---  

Connect this pin to a Non-volatile battery power source in the range of 1.2V - 3.0V when using design security volatile key. In this case, do not connect this pin to a volatile power source on the board. 3.0V is the typical battery power selected for this supply. When not using the volatile key, tie this to a 1.5V, 2.5V or 3.0V supply. Cyclone V devices will not exit POR if VCCBAT stays at logic low. 

--- Quote End ---  

Altera_Forum
Honored Contributor I
94 Views

i fixed vccbat but i havnt dclk yet unfortunately  

my power supply can be wrong?
Altera_Forum
Honored Contributor I
94 Views

 

--- Quote Start ---  

power up 

Power up all the power supplies that are monitored by the POR circuitry. All power supplies, including VCCPGM and VCCPD, must ramp up from 0 V to the recommended operating voltage level within the ramp-up time specification. Otherwise, hold the nCONFIG pin low until all the power supplies reach the recommended voltage level. 

--- Quote End ---  

 

 

You should consider to select standard POR delay (100 ms) instead of fast (4 ms) in MSEL if you have problems with power supply ramping. 

 

I remember there have been problems with previous Cyclone families and non-monotonous power supply startup which could cause wrong latching of MSEL coding under circumstances. Not sure if it could still occur with Cyclone V. Nevertheless I would check all power supplies statically and dynamically.
Altera_Forum
Honored Contributor I
94 Views

everything seems ok 

except my power sequence  

first my 1.1 voltage came after that 3.3 and after that 2.5 voltage comes  

is that right?
Altera_Forum
Honored Contributor I
94 Views

You can refer to the datasheet to know about the power sequence. 

First the 1.1V is applied, then other supplies. 

But I think it should work with any power on sequence. 

 

BUT in the schematic, you left the rref_tl floating. It should be connected through 2KOhm resistor to the gnd. I faced this issue before and the PLLs of the FPGA did not work till I fixed this RREF_TL pin. 

I don't know if RREF_TL affects the dclk or not. BUT it will surely affect the PLLs of the FPGA. Don't you intend to use the PLLs?
Altera_Forum
Honored Contributor I
94 Views

thank you for your reply 

i redesign my FPGA board 

i fixed vccbat and pref_tl 

but one think i want to know tramp of power is important? 

should i care about tramp?
Altera_Forum
Honored Contributor I
94 Views

According to my experience, power sequence and ramping isn't particularly critical with Cyclone V. But in case of doubt you should keep the device handbook recommendations. 

 

RREF_TL is exclusively used by Gbit-Transceivers. The suggested connection for non-GX devices in the Quartus *.pin File and Pin Connection Guidelines is GND. I don't expect actual problems when leaving it unconnected, but I didn't try.
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