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Valued Contributor III
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PCI Express on Cyclone V GT FPGA Development Kit

Hi, everyone! I have a problem with devkit -- https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-gt.html 

 

I tried to connect the board to PC and run reference designs (one - http://www.alterawiki.com/wiki/reference_design:_gen2x4_avmm_dma_with_external_ddr3_-_cyclone_v, two - http://www.alterawiki.com/wiki/reference_design:_gen2x4_avmm_dma_-_cyclone_v

 

I try to run Gen1 x4 on two PC, but stuck on link training.  

 

On one PC when used Gen3 x8 slot ltssm stoped on Polling.Active state. When used Gen3 x4 slot ltssm stoped on Config.Linkaccept, but lane_act = 4’b1000 that means x8, as far as I can see.  

 

On other PC when used Gen3 x16 slot ltssm stoped on Polling.Active state. 

 

Why could be a problem?
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