I am trying to sortout an issue I am seeing with power up level of IO pins on a Cyclone 5 board. I had thought that all IO were tristated until the user design was configured. However, when reading thru https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cfg/cfg_cf51001.pdf I am not sure if I am reading it right. It says:
"Before and during configuration, all user I/O pins are tristated. Stratix® series, Arria® series, and Cyclone® series have weak pull-up resistors on the I/O pins which are on, before and during configuration."
Then later says: "After entering user mode, the user I/O pins will no longer have a weak pull up and will function as assigned in your design. "
If the pins are tristated what is the purpose of the weak pullup as wouldnt any external devices see the pins as floating as opposed to logic high? Are the pins released from tristate prior to the weak pullups being disabled and user design being ready?