Configuration Qsys to DDR3 of FPGA on the Cyclone V SoC Development Kit Board

[Altera_Forum]

Hello, 

 I'm using a Cyclone V SoC Development Kit Board.   I created a "DDR3 SDRAM Controller with UniPHY" on Qsys(Quartus 14.1) for DDR3 of FPGA side. But, I can't access DDR3 from h2f_axi_master. HPS locked for DDR3 access on h2f_axi_master .   Maybe, I think mistake my configuration(parameter) to Qsys for DDR3 of FPGA side. Please teach me a configuration(parameter) to Qsys for DDR of FPGA side.  Best Regards, Hidemi Ishihara.

[Altera_Forum]

There are a series of things that should happen: 

 1) The bridge is pulled out of reset 2) The bridge receives an active clock 3) The bridge is mapped into the HPS memory space (see remap register in the system manager) 4) Processor MMU is configured to allow processor transactions to the H2F bridge  If one of those steps is skipped then you'll either end up with a bus error (#3 and# 4) or the transaction will not complete and there is no bus error (#1 and# 2). I think the preloader sets up# 1 and# 2 for you and configuring the FPGA probably sets up# 3 but I would run some tests to make sure that by the time you attempt to access the FPGA all of these steps have completed first.