Honored Contributor II
04-04-2018 10:25 AM
Hello,My design - targeted for an Arria V GX FPGA requires an 8b/10b encoded single lane transceiver operating at 1.868 GHz. I decided to use the Native Tranciever Phy for this purpose: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/xcvr_user_guide.pdf On the Tx side I'd like to send 2 bytes per a 93.44 MHz clock. The document in the above link mentions that tx_parallel_data is 44 bits wide. At page# 272 table 10-13 describes a possible double byte configuration that would allow me to achieve the desired configuration. It's called: "Double word data bus, byte serializer disabled". Unfortunately, I can't find a way to configure the core to use this configuration...