Confused: Can FPGA measure less than 0.1ns delay between digital pulses?

[Tufts]

Hello! I am a beginner of FPGA and want to learn can I build FIR-like structures in FPGA to process multi-channels of high speed pulse train and detect less than 0.1ns delay between each pulse? 

I find the Intel Agilex 9/Stratix 10 AX can perform direct analog RF signal conversion for multiple analog input and output channels at groundbreaking rates as fast as 12 gigasamples/sec (Gsps) over sixteen channels, and 64 Gsps over as many as eight channels. However, the internal clock rate is much less (only 1000MHz at most for Stratix 10).  I am confused why the built-in RF ADC and DAC in Stratix 10 are claimed to operate as fast as 64 Gsps with 36 GHz of input bandwidth? If the internal clock rate is only 1GHz, how do FPGA logic cells process 10s of GHz output data from the built-in ADC/DAC?

I think I am confused about the Clock speed, Max IO speed and the Max Sampling speed of FPGA. Can any one give me some advices? Thank you very much!

[_AK6DN_]

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can I build FIR-like structures in FPGA to process multi-channels of high speed pulse train and detect less than 0.1ns delay between each pulse?

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Not going to happen. Not in any existing FPGA. Would be difficult to do even in an ASIC.

If you design some logic, controlling the delays to such accuracy is not within the realm of existing layout tools.
You would need to go to a fully manual placement and routing.
And probably a spice-level timing simulation to validate your design works as expected.
The simple timing analyzer tools provided for FPGA timing analysis are insufficient for such an analysis.

Given the maximum clock rates in the 500MHz to 1GHz range you can not process 10GHz (ie, 100ps) signals.

The existing technology is one to two orders of magnitude slower than your requirement.

[WZ2]

Hi there,

1.      Clock Speed: The input clock speed of an FPGA determines how fast the logic cells inside the FPGA can operate. This clock speed is used for internal processing and can be much lower than the data rates you mentioned (e.g., 1 GHz).

2.      Max IO Speed: This refers to the maximum rate at which data can be transferred between the FPGA and external devices, like memory, other chips, or ADC/DAC. It's usually lower than the internal clock speed due to the overhead involved in data transfer.

3.      Max Sampling Speed: This pertains to the maximum rate at which an ADC can sample incoming analog signals, and similarly, the maximum rate at which a DAC can convert digital data to analog. The high sampling rate you mentioned (e.g., 64 Gsps) represents the raw data rate at the analog level.

Best regards,

WZ