Connect differential input clock with the pll

[Altera_Forum]

How can I connect a differential clock input to the PLL?,i was trying to find a example , but they shows example using a LVDS interface, but i couldn't see how connect the differential clock input to the PLL in Quartus II, It has something to do with the RSDS?

[Altera_Forum]

Select a supported differential I/O standard (e.g. LVDS) for the positive pin of the differential clock input pair in Pin Planner. The negative pin will be selected automatically.

[Altera_Forum]

Yes, FvM is correct. The PLL's only allow the specific clock IO's to be use with out warnings. But those clocks are capable of of differential signaling. 

 Make sure if you are designing your own board, and require multiple PLL's you use the correct clock input pins for different PLL's in the system. IE: Typically each pll, has 4 possible clock inputs, so ALL clock inputs can not drive ALL PLL's. (with out warnings and non-optimized skew and jitter at least).  Pete

[Altera_Forum]

Hello,  

 since I am trying to do the same thing, I would like to make a question about the dedicated pins. I am working with a TR4 Board from Terasic, based on the Stratix IV EP4SGX530KH40C2 FPGA chip. I am actually assigning the input of my PLL to a pin which should be appositely dedicated to a clock input (differential and configured in LVDS mode), they correspond to W35 and W34 (page3/20: http://www.altera.com/literature/dp/stratix4/ep4sgx530.pdf). This 2 pins are connected to differential clock inputs on a HSMC connector. In my design I define these pins as LVDS, and I just assign the positive one to the input of the PLL.  Everytime I compile the design, even if I have added an assignment specifying that this clock is a global signal, I get always a warning about the jitter due to non dedicated routing.  Warning (15056): PLL "PLL_Block:b1|altpll:altpll_component|PLL_Block_altpll:auto_generated|pll1" input clock inclk[0] may have reduced jitter performance because it is fed by a non-dedicated input  Info (15024): Input port INCLK[0] of node "PLL_Block:b1|altpll:altpll_component|PLL_Block_altpll:auto_generated|pll1" is driven by HSMD_CLKIN_p1~inputclkctrl which is OUTCLK output port of Clock enable block type node HSMD_CLKIN_p1~inputclkctrl  Did I maybe misunderstood the data sheet? Or is there some other step to do such as other particular assignments to force Quartus II fitting this pin with an optimized route?

[Altera_Forum]

Yes, I've tried , and it is, thanks 

 Another point, if I can use the input clock as a single-ended input clock, can I use the other pin as a user I/O?  thanks in advance

[Altera_Forum]

--- Quote Start ---  Yes, I've tried , and it is, thanks  Another point, if I can use the input clock as a single-ended input clock, can I use the other pin as a user I/O?  thanks in advance  --- Quote End ---    It depends on your FPGA, you may have a look at the specifications, for example in Stratix IV, the pins I am using to send in the differential clock are defined on the data sheet as IO or optionally as dedicated clock inputs. Try to have a look at the pin out information for your FPGA, which FPGA are you using?

[Altera_Forum]

I'm Using a Cyclone IV, EP4CE75, I'm designing a board with this chip and i need more pins, so I'm planing use the input clock (the positive pin) and the anoher as user input.

[Altera_Forum]

I've cheked in this file "Cyclone IV Device Family Pin Connection Guidelines" and it says : 

"Dedicated global clock input pins that can also be used for the positive terminal inputs for  differential global clock input or user input pins.  In Cyclone IV GX devices, some of these pins are optional high speed differential reference clock  positive input" , so i can use it as a input, great !! :D, thanks to everybody for help me

[Altera_Forum]

But, Does it mean, one can be input clock and the another pins can be a input user???

[Altera_Forum]

But, Does it mean, one can be input clock and the another pins can be a input user???

[Altera_Forum]

My Experience, is yes, it can be used as a general input. Some of the families support it being used as a general IO/ but not all. 

 Pete