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noria
Beginner
316 Views

Connection of pll_ref_clk in an Arria10 with one JESD204b receiver

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I am using an Arria10 and I implement one JESD204b receiver to communicate with one ADC which has the following paramters LMF=422.

According to the user guide I should connect to the pll_ref_clk, the output of of an ATX_PLL. However when doing this, the tools complains that this is not feasible and require connection of the reference clock (from the pin) straight. Thus two questions:

  • Is this correct?
  • If yes, then what the ATX_PLL is for (since I have only one receiver over four lanes and no bonding clock connection is offer at the IP ports)

Thanks

Nicolas

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Accepted Solutions
noria
Beginner
37 Views

HI

Well the page 66 of the JESD204B IP specify that the transceiver PLL need to be out of the transceiver for Arria10 device (the one I am using).

Regards

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3 Replies
Rahul_S_Intel1
Employee
37 Views

Hi ,

May I know where you find in the document ATX_PLL output to pll_ref_clk. The reference clock has to be connected from the dedicated clk input pins

noria
Beginner
38 Views

HI

Well the page 66 of the JESD204B IP specify that the transceiver PLL need to be out of the transceiver for Arria10 device (the one I am using).

Regards

View solution in original post

Rahul_S_Intel1
Employee
37 Views

Hi ,

Can you please check the upstream PLL ( that is the pll driving the ATX pll) you have the option provided as cascade.

 

JESD user guide

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-design-ex-jesd204b.pd...