I am using an Arria10 and I implement one JESD204b receiver to communicate with one ADC which has the following paramters LMF=422.
According to the user guide I should connect to the pll_ref_clk, the output of of an ATX_PLL. However when doing this, the tools complains that this is not feasible and require connection of the reference clock (from the pin) straight. Thus two questions:
- Is this correct?
- If yes, then what the ATX_PLL is for (since I have only one receiver over four lanes and no bonding clock connection is offer at the IP ports)
May I know where you find in the document ATX_PLL output to pll_ref_clk. The reference clock has to be connected from the dedicated clk input pins
Can you please check the upstream PLL ( that is the pll driving the ATX pll) you have the option provided as cascade.
JESD user guide