Constraining DDR inputs

[Altera_Forum]

I'm working on an FPGA design which interfaces to a DDR ADC chip. I need to apply constraints to the ADC data and clock input ports. First I have a question about virtual clocks: It seems to me that a virtual clock is just a convenience to simplify specifying the min and max delays. If the virtual clock is in phase with the port clock there is no point to using a virtual clock. Is this correct? 

 Secondly, I would really appreciate some help on how to setup the timing constraints for interfacing to a DDR input device like the ADC. It seems to me that TimeQuest doesn't really understand DDR at all and you have to fake it by using timing exceptions. Simply setting up min and max delays for a DDR input leads to erroneous timing violations because it doesn't understand data changes at 1/2 clock cycles.

[Altera_Forum]

Please take a look at this document: 

http://www.alteraforum.com/forum/showthread.php?p=19264

[Altera_Forum]

Thanks, this was way more helpful than Altera's course on DDR timing constraints.

[Altera_Forum]

Thank Rysc instead. :) 

 Regarding virtual clocks, they're also useful because the "real" clock in the FPGA and the "virtual" clock at the ADC can have different uncertainties (jitter, etc). In particular, if you use the "derive_clock_uncertainty" command (which you should...), you should use virtual clocks to get the correct results. So, as a rule of thumb, do use virtual clocks.