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Constraining TSE IP while using with external PhY on DE4 boards

Altera_Forum
Honored Contributor I
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Hi All; 

 

I have been trying to get a DE4 board to connect to a PC or a router using Nichestack TCP/IP stack and Ethernet cable. 

 

Auto negotiation with router/PC passes but then no more progress. The Design can't get an IP from the router and when I set a static IP I can't ping the FPGA. The rx LED on the Ethernet port blinks but the tx LED rarely does so. 

 

Several older threads associate this behaviour with timing constraints. I include the auto-generated SDC file that comes with the TSE in the project, and constrained the main clock. Then I derive the PLL clocks and clock uncernaties. When it comes down to the virtual clock, I need the tsu and other timing parameters of the Marvell 88e1111 PHY chip that is located on the DE4 board and I am using. However all that I get is some physical dimensions from the "Datasheet" provided my Marvell- 88e1111 PHY prodect brief.  

 

I would appreciate it if some one could help me get the timing parameters for the Marvell PHY chip or a more useful datasheet. Or is there something that I am missing altogether ? 

Has anyone been able to get the simple socket server running properly on DE4 board using Quartus prime 16.0 ?  

 

Thanks
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