Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
776 Views

Constraining generated clock having as source output pin

Hello, 

 

I am working on an Arria10 FPGA from Altera making use of the PHY transceiver. For my project, the reference clock of the transmit PLL has to be synchronous to the recovered clock from the CDR. 

The rxoutclk goes to an output pin of the FPGA, which goes to an external PLL and this PLL drives the input ref clock of the transceiver. 

I am trying to create a generated clock contraint: create_generated_clock -source [get_ports {SMA_CLK_OUT}] -divide_by 1 [get_ports {REFCLK1_P}] 

However, the tool displays the following message: No paths exist between clock target "REFCLK1_P" of clock "REFCLK1_P" and its clock source. 

 

I would like to constrain this clock as a generated clock in order to properly perform timing analysis on CDC between rxoutclk and txoutclk (automatically generated by the tool from the reference clocks) 

 

Does anyone know how to properly set the generated clock constraint so the generated clock is properly propagated? 

 

Eduardo
0 Kudos
0 Replies
Reply