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Constraining multi-phase clock oversampling circuit

Altera_Forum
Honored Contributor II
‎01-06-2015 12:35 PM
1,075 Views

Hi all,  

 

I am implementing an oversampling circuit using multi-phase clocks. For each  

clock the input signal passes through a 2-FF synchronizer, than the sampled  

value is pushed into a FIFO of depth 2. The FIFOs are read with the base clock  

(phase 0) and all further processing is done with this clock. What is the  

proper way of constraining such circuit? Treat the clocks as unrelated or  

use multicycle paths? I feel multicycle may be better, since I need to also  

implement and constrain the reset/enable synchronization. 

 

Thanks for your help.
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