Constraints from LVDS blocks and logic

[Altera_Forum]

Hi, 

 I have a lvds tx and rx blocks in a Stratix3. There a 20 bits with deserialisation factor of 4. With the Rx side, the data leaving the lvds is registered. The lvds and registers are using clocks from a PLL.  TimingQuest gives me an erro and show the sclkout rising edge as the source clock but with the rising edge of the register clock directly underneath. I've used the write sdc command and got the lvds constraints it generates. However, they just don't seem to cover this path between the sclkout and the registers. I would have though that the hold time would have been 4 sclks.  I do have a clock mux on a couple of outputs from the PLL and it's the output of the mux that drives the registers. I don't know if this is cause a problem or not.  If I put a hold time of 2, then problem goes away but is TimingQuest highlighting a problem?  Regards  MT

[Altera_Forum]

Thanks Rysc. 

 I did signal tap the data straight out of the lvds block and also out of the registers, and it was going wrong out of the lvds block. I've managed to get something working by tweaking the lvds sclk phase and enable. But on top of this, I changed the DPA settings so that it's using the rising and falling edges of the clock. This is also helped nudge it in the right direction.  I tried adding the clock uncertainty and it didn't make any difference to the results. I also tried changing the constraints but it didn't help either. With the hold error, what it's telling me is that launch clock is getting there very quickly and the latch clock is much slower, hence the hold error. The all paths setting fixes is it for now but I'm not sure what more can be done with this.  What I'm finding from the main build (which uses TAN and this lvds section gets intergrated into it) is that it still seems to try, for example, to meet a 1.6ns (625MHz) timing requirement from the registers in the fabric to the tx lvds registers when the multi-cycle constraints say that the setup time is 3 clocks. I have no idea why it's trying to do this. I don't know if it's trying to do the same with the rx side too. Any idea's why this might be the case? Is it because I've changed the sclk phase in both the rx and tx lvds blocks?  I've added a set of multi-cycle constraints which I translated from TimingQuest. I know these are supposed to built-in but the above seems to suggest it's ignoring them. Maybe that's why there is a hold error too.