Converting Shift registers to memory

[Altera_Forum]

Hi 

I am trying work with Shift registers and want them to be implemented with the STRATIX memory  How can I do that ? and how can I check in the Quartus reports that it was done.   When I create the S.R. it takes not to meny LCs but when I try to connect the S.R. last stage somewhere the LC usage becomes too big to fit the device, why is that?     (* ramstyle = "M4K" *) reg [2677:0] RefBuff[15:0]; (* ramstyle = "M4K" *) reg [2677:0] InLine[15:0]; //S.R. for the incoming data (* syn_ramstyle = "M4K" *) reg [2677:0] Line_Buff[15:0];     //################ InData to Shift Reg# #########################    always@(posedge Rx_clk_A)  begin  InLine[0] <= l[15:0];  end        always@(negedge Rx_clk_A)   begin   if ( write_port_A )   begin  for (I=0 ; I<15 ; I=I+1)  begin  InLine[I+1] <= InLine[I];    end   end  end

[Altera_Forum]

If you don't connect the shift register output, the register isn't implemented by the compiler, so it consumes neither RAM nor logic cells. 

 The question is, why your shift register apparently isn't inferred in RAM by the compiler. The usage of two individual always block may be the reason, but I'm not sure about. If inference doesn't work, you can instantiate a ALTSHIFT_TAPS MegaFunction explicitely.  The implementation can be traced in the resource section of the fitter report. Also the hierarchy display shows all inferred RAM and register count per entity.

[Altera_Forum]

Thanks, 

 I will try that and tell you how it went   :D