CoreSight ETR (Embedded Trace Router) readable from Linux

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

CoreSight ETR (Embedded Trace Router) readable from Linux

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Hello, I have two questions regarding the ARM CPU (HPS) in the Cyclone V boards. 1.) Do only the Cyclone V S[x] products have the ARM CPU on board? (Table "The Family Comes in Six Targeted Variants" at http://www.altera.com/devices/fpga/cyclone-v-fpgas/cyv-index.jsp seems to suggest so) 2.) Is it possible to configure the CoreSight ETM (embedded trace macrocell) in ETR (embedded trace router) mode to store instruction/data traces to main system memory and retreive the recorded traces from linux? thank's for your answers/pointers --m

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