Could not find rtl_work.TB.vhd

[Altera_Forum]

Hello,  

 The same process is giving issues once again: # ** Error: (vsim-3170) Could not find 'C:\Users\Alfonso\Desktop\PFC\simulation\modelsim\ rtl_work.TB_PFC_main'.# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./PFC_run_msim_rtl_vhdl.do PAUSED at line 34   I remember to delete the work folder to be able to compile a library that need that according to a modelsim tutorial: http://doc.union.edu/118/se_tutor.pdf (http://doc.union.edu/118/se_tutor.pdf)   I have to do  vcom <vhdl files .vhd> # do this for all the files  cause it had to be done in the work folder, this may have caused the issue.   i'm lost, can anyone help me?.

[Altera_Forum]

Please, can anyone help me?

[Altera_Forum]

--- Quote Start ---  Please, can anyone help me?  --- Quote End ---  The VHDL code is trying to use a component compiled into the rtl_work library. You can either compile your code into rtl_work via;  vsim> vlib rtl_work vsim> vmap rtl_work [pwd]/rtl_work vsim> vcom -work rtl_work <your VHDL files>  or you can simply map the rtl_work library to the same location as the work directory, eg., assuming you have created your work directory in the same folder you are working in via  vsim> vlib work vsim> vmap work [pwd]/work  then you can tell Modelsim to look in the work directory for the rtl_work components too by mapping it via  vsim> vmap rtl_work [pwd]/work  (You don't need the [pwd] statement if you don't want to use absolute paths in your .ini or .mpf file).  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  The VHDL code is trying to use a component compiled into the rtl_work library. You can either compile your code into rtl_work via;  vsim> vlib rtl_work vsim> vmap rtl_work [pwd]/rtl_work vsim> vcom -work rtl_work <your VHDL files>    --- Quote End ---    Hello,   by typing this, how do you fill <your vhdl files>, by typing my vhdl files root (C:\Users\Alfonso\Desktop\PFC\altera) returns this:   (I typed vsim> vcom -work rtl_work C:\Users\Alfonso\Desktop\PFC\altera) # Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011# ** Error: (vcom-7) Failed to open design unit file "C:UsersAlfonsoDesktopPFCltera" in read mode.# Invalid argument. (errno = EINVAL)# E:/altera/11.1sp2/modelsim_ase/win32aloem/vcom failed.    --- Quote Start ---    or you can simply map the rtl_work library to the same location as the work directory, eg., assuming you have created your work directory in the same folder you are working in via  vsim> vlib work vsim> vmap work [pwd]/work  then you can tell Modelsim to look in the work directory for the rtl_work components too by mapping it via  vsim> vmap rtl_work [pwd]/work  (You don't need the [pwd] statement if you don't want to use absolute paths in your .ini or .mpf file).  Cheers, Dave  --- Quote End ---    It did not work, assuming [pwd] is written as [pwd] litterally (if it is a root instead, tell me) after typing those three lines literally as you did it continues returning me: # ** Error: (vsim-3170) Could not find 'C:\Users\Alfonso\Desktop\PFC\simulation\modelsim\rtl_work.TB_PFC_main'.# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./PFC_run_msim_rtl_vhdl.do PAUSED at line 34   Please help me i cannot test my code till this is solved.

[Altera_Forum]

--- Quote Start ---   by typing this, how do you fill <your vhdl files>, by typing my vhdl files root (C:\Users\Alfonso\Desktop\PFC\altera) returns this:   (I typed vsim> vcom -work rtl_work C:\Users\Alfonso\Desktop\PFC\altera)   --- Quote End ---    You've passed it a directory, not a VHDL file. You need to pass the vcom command the files that end in .vhd. You need to compile all of your files into the work library. If you are using Modelsim-ASE, then you do not need to compile Altera libraries.  Cheers, Dave

[Altera_Forum]

Thank you for the effort. 

 I typed:  ... vcom -work rtl_work fixed_float_types_c.vhdl  and it returned: # Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011# ** Error: (vcom-7) Failed to open design unit file "fixed_float_types_c.vhdl" in read mode.# No such file or directory. (errno = ENOENT)# E:/altera/11.1sp2/modelsim_ase/win32aloem/vcom failed.  I moved from desktop to D: and tried again but failed with the same code, i try giving them write licence to all project files and folders, also with that failed.  Alfonso.

[Altera_Forum]

Hi Alfonso, 

  --- Quote Start ---   I typed:  ... vcom -work rtl_work fixed_float_types_c.vhdl  and it returned: # Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011# ** Error: (vcom-7) Failed to open design unit file "fixed_float_types_c.vhdl" in read mode.# No such file or directory. (errno = ENOENT)# E:/altera/11.1sp2/modelsim_ase/win32aloem/vcom failed.  I moved from desktop to D: and tried again but failed with the same code, i try giving them write licence to all project files and folders, also with that failed.  --- Quote End ---  Try reading the output from Modelsim - it says that it cannot find the file.  So where is fixed_float_types_c.vhdl located? If its not in the same directory as Modelsim is currently located, then you have to supply the full path to the file. For example, something like  vsim> cd c:/temp vsim> vlib rtl_work vsim> vmap rtl_work rtl_work vsim> vcom -work rtl_work c:/vhdl/ieee_fixed_pkg/fixed_float_types_c.vhdl  Cheers, Dave

[Altera_Forum]

Hello, 

 Seems all of this work, But:   when i copy fixed_pkg_c.vhdl & fixed_float_types_c.vhdl now everything goes ok!   vcom -work rtl_work fixed_float_types_c.vhdl# Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011# -- Loading package STANDARD# -- Compiling package fixed_float_types vcom -work rtl_work fixed_pkg_c.vhdl# Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011# -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Loading package NUMERIC_STD# -- Loading package fixed_float_types# -- Compiling package fixed_pkg# -- Loading package MATH_REAL# -- Compiling package body fixed_pkg# -- Loading package fixed_pkg# ** Warning: [3] fixed_pkg_c.vhdl(1470): (vcom-1246) Range 0 downto 1 is null.# ** Warning: [3] fixed_pkg_c.vhdl(1471): (vcom-1246) Range 0 downto 1 is null.# ** Warning: [3] fixed_pkg_c.vhdl(1472): (vcom-1246) Range 0 downto 1 is null.# ** Warning: [3] fixed_pkg_c.vhdl(6888): (vcom-1246) Range 2 to 1 is null.      but if i close the modelsim and launch it (even having compiled again) reappears the error:     # ** error: (vsim-3170) could not find 'c:\users\alfonso\desktop\pfc\simulation\modelsim\ rtl_work.tb_pfc_main'.# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./PFC_run_msim_rtl_vhdl.do PAUSED at line 34  how do i do to save the results??  To launch ok modelsim i've got to close the console and reestart the modelsim, wich takes me to # ** error: (vsim-3170) could not find 'c:\users\alfonso\desktop\pfc\simulation\modelsim\ rtl_work.tb_pfc_main'.  Thank you!!

[Altera_Forum]

--- Quote Start ---   but if i close the modelsim and launch it (even having compiled again) reappears the error:  # ** error: (vsim-3170) could not find 'c:\users\alfonso\desktop\pfc\simulation\modelsim\ rtl_work.tb_pfc_main'.# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./PFC_run_msim_rtl_vhdl.do PAUSED at line 34   --- Quote End ---   But here you are doing something completely different - you are running a Tcl scope called PFC_run_msim_rtl_vhdl.do  If you want to use the fixed-point package and use that Tcl script, you need to read the script to determine how it configures the library mappings. Most likely you can just add the lines to compile the fixed-package into rtl_work into that Tcl script.  Cheers, Dave

[Altera_Forum]

What's the TCl script??? , if i modify the PFC_run_msim_rtl_vhdl.do (Tcl scope) by adding: 

 vcom -work rtl_work fixed_float_types_c.vhdl vcom -work rtl_work fixed_pkg_c.vhdl  It does overwrite and here we are again.  What have i to modify? (Tcl script) What's this?

[Altera_Forum]

--- Quote Start ---  What's the TCl script???   --- Quote End ---    Its your design, you tell me!    --- Quote Start ---   if i modify the PFC_run_msim_rtl_vhdl.do (Tcl scope) by adding:  vcom -work rtl_work fixed_float_types_c.vhdl vcom -work rtl_work fixed_pkg_c.vhdl  It does overwrite and here we are again.  What have i to modify? (Tcl script) What's this?  --- Quote End ---    If you do not know what a Tcl script is, then you need to go through some of the Modelsim documentation. Tcl = Tool Command Language, and its the language used to script (automate) the Quartus and Modelsim tools.  Cheers, Dave

[Altera_Forum]

Hello and thank you for your involvement, i don't know how to make a permanent configuration of tcl commands, according to se_tutor (http://www.alteraforum.com/forum/se_tutor) chapter 14, Tcl commands are what we were typing on the modelsim console, but i've not found nothing talking about scripts. 

 Please help me i must have debugged my code for next wednesday, and i can't use modelsim due to errors.   PS: one thing if I use notepad++ to modify a .DO file, launching modelsim overwites it, so i don't know how to make permanent changes.  (http://www.alteraforum.com/forum/se_tutor)

[Altera_Forum]

--- Quote Start ---  Hello and thank you for your involvement, i don't know how to make a permanent configuration of tcl commands, according to se_tutor (http://www.alteraforum.com/forum/se_tutor) chapter 14, Tcl commands are what we were typing on the modelsim console, but i've not found nothing talking about scripts.   --- Quote End ---    Scripts are just files that you run (source) in the Modelsim console. Basically you're just saving yourself some typing.    --- Quote Start ---   Please help me ...   --- Quote End ---   I'm trying, but you appear to be missing some fundamental experience with these tools ... so lets see if we can fix that.    --- Quote Start ---   PS: one thing if I use notepad++ to modify a .DO file, launching modelsim overwites it, so i don't know how to make permanent changes.   --- Quote End ---   I've never seen Modelsim overwriting files. How are you starting Modelsim? If you are starting Modelsim from Quartus, then it is probably Quartus that is modifying files, not Modelsim.  Please review the modelsim_example.zip tutorial on using Modelsim posted in this thread:  http://www.alteraforum.com/forum/showthread.php?t=32386  That example shows what a Modelsim Tcl script is.  Please explain the steps you are performing with Quartus and Modelsim to have the problem with overwriting files.  Cheers, Dave

[Altera_Forum]

Good afternoon/Morning: 

 What i try to do is:  1st:  vcom -work rtl_work fixed_float_types_c.vhdl  vcom -work rtl_work fixed_pkg_c.vhdl  2nd they work as yesterday did then i close the console, cause if the console is stoped i cannot launch MS succesfully, and when i press the button rtl compilation (> and a register with a timing signal under > and the reg) it launches and then after a while:  # ** error: (vsim-3170) could not find 'c:\users\alfonso\desktop\pfc\simulation\modelsim\rtl_work.tb_pfc_main'.# error loading design# error: error loading design # pausing macro execution # macro ./pfc_run_msim_rtl_vhdl.do paused at line 34      or   Same happens if i launch pfc_run_msim_rtl_vhdl.do with nottepad ++ and write, save and close, and then launch rtl compilation:  ------------------------------------------------------------------- transcript on if {[file exists rtl_work]} {  vdel -lib rtl_work -all } vlib rtl_work vmap work rtl_work  vcom -work rtl_work fixed_float_types_c.vhdl  vcom -work rtl_work fixed_pkg_c.vhdl  vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/IHW_UART.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/altera/fixed_float_types_c.vhdl} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/PLL.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/altera/fixed_pkg_c.vhdl} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/Pack.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteS.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteE.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteO.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/SumaStep.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProdAnteriorNE.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProdAnteriorNO.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProdAnteriorSO.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProdAnteriorSE.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteSE.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteSO.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteNO.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteNE.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/ProducteN.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/CNN.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/PFC_main.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/SumaStep1.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/SumaStep2.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/SumaStep3.vhd}  vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/TB_PFC_main.vhd}  vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneii -L rtl_work -L work -voptargs="+acc" TB_PFC_main  add wave * view structure view signals run -all -------------------------------------------------------------------  It is deleted which leads me to:  # ** error: (vsim-3170) could not find 'c:\users\alfonso\desktop\pfc\simulation\modelsim\rtl_work.tb_pfc_main'.

[Altera_Forum]

Hello, this is the testbench file i want to use, i'm planning to use this, in case you need to know it. 

 Alfonso

[Altera_Forum]

Look at the Tcl script again. It already has the lines: 

  vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/altera/fixed_float_types_c.vhdl} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/PLL.vhd} vcom -93 -work work {C:/Users/Alfonso/Desktop/PFC/altera/fixed_pkg_c.vhdl}   Note how the code is being compiled into the library work.  Since it sounds like you are using Quartus to run Modelsim, use Quartus to change the library those two packages are compiled into, eg., right click on the files, and set the library to rtl_work (I think that is how you do it).  Alternatively, just edit the VHDL files and change rtl_work to just plain work, and then it'll work fine.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---    Since it sounds like you are using Quartus to run Modelsim, use Quartus to change the library those two packages are compiled into, eg., right click on the files, and set the library to rtl_work (I think that is how you do it).   --- Quote End ---    Leads to quartus compilation error:  Error (10481): VHDL Use Clause error at ProducteN.vhd(4): design library "ieee_proposed" does not contain primary unit "fixed_pkg" Error (10800): VHDL error at ProducteN.vhd(4): selected name in use clause is not an expanded name Error (10481): VHDL Use Clause error at Pack.vhd(10): design library "ieee_proposed" does not contain primary unit "fixed_pkg" Error (10800): VHDL error at Pack.vhd(10): selected name in use clause is not an expanded name Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 4 errors, 1 warning  Error: Peak virtual memory: 316 megabytes  Error: Processing ended: Thu Sep 13 18:56:45 2012  Error: Elapsed time: 00:00:02  Error: Total CPU time (on all processors): 00:00:02 Error (293001): Quartus II Full Compilation was unsuccessful. 6 errors, 1 warning  I'm trying the alternative method.  PS: Properties->library-> rtl_work, if i return to erase rtl_work from the Properties->library-> rtl_work, quartus compilates ok.

[Altera_Forum]

--- Quote Start ---   Alternatively, just edit the VHDL files and change rtl_work to just plain work, and then it'll work fine.  Cheers, Dave  --- Quote End ---    Sorry neither fixed_float_types_c fixed_pkg_c contains the rtl_work name, and if you refered to PFC_run_msim_rtl_vhdl.vhdl changes, it erases them.  Alfonso.

[Altera_Forum]

If you referd to "change the library those two packages are compiled into, eg., right click on the files, and set the library to rtl_work" -> work 

 work leads to same situation as nothing there.

[Altera_Forum]

--- Quote Start ---  Leads to quartus compilation error:  Error (10481): VHDL Use Clause error at producten.vhd(4): design library "ieee_proposed" does not contain primary unit "fixed_pkg" Error (10800): VHDL error at producten.vhd(4): selected name in use clause is not an expanded name Error (10481): VHDL Use Clause error at pack.vhd(10): design library "ieee_proposed" does not contain primary unit "fixed_pkg" Error (10800): VHDL error at pack.vhd(10): selected name in use clause is not an expanded name Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 4 errors, 1 warning  Error: Peak virtual memory: 316 megabytes  Error: Processing ended: Thu Sep 13 18:56:45 2012  Error: Elapsed time: 00:00:02  Error: Total CPU time (on all processors): 00:00:02 Error (293001): Quartus II Full Compilation was unsuccessful. 6 errors, 1 warning  I'm trying the alternative method.  PS: Properties->library-> rtl_work, if i return to erase rtl_work from the Properties->library-> rtl_work, quartus compilates ok.  --- Quote End ---    THIS ERROR IS POINTING TO MY PROJECT FILES INCLUDES!! But once again about ieeeproposed...  The pack file is this:   -------------------------------------------------------  -- Design Name : User Pakage  -- File Name : Pack.vhd  -- Function : Defines function for LFSR  -- Coder : Alexander H Pham (VHDL)  ------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library ieee_proposed; use ieee_proposed.fixed_pkg.all; USE ieee.std_logic_arith.all; use IEEE.std_logic_unsigned.all;     package Pack is   type info is array (1 to 78) of sfixed (1 downto -16);-- 78= 8*8 + 14/16 bordes  type templates is array (1 to 9) of sfixed (1 downto -16);   end;    package body Pack is      end package body;  But also my main includes:  library ieee_proposed; use ieee_proposed.fixed_pkg.all;  with no error.

[Altera_Forum]

VHDL allows you to package components into libraries. 

 If you know how to use the tools, then its relatively easy to get libraries working. Since you are letting the tool create scripts for you, its a little harder.  To make your life simpler, just edit the VHDL files with   library ieee_proposed; use ieee_proposed.fixed_package.all;  and change these two lines into the single line  use work.fixed_package.all;  Then both Quartus and Modelsim will look for all VHDL in the default work library.  Cheers, Dave