Could not find rtl_work.TB.vhd - Page 3

Altera_Forum · ‎09-11-2012

Hello,

The same process is giving issues once again:

# ** Error: (vsim-3170) Could not find 'C:\Users\Alfonso\Desktop\PFC\simulation\modelsim\ rtl_work.TB_PFC_main'.# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./PFC_run_msim_rtl_vhdl.do PAUSED at line 34

I remember to delete the work folder to be able to compile a library that need that according to a modelsim tutorial: http://doc.union.edu/118/se_tutor.pdf (http://doc.union.edu/118/se_tutor.pdf)

I have to do

vcom <vhdl files .vhd> # do this for all the files

cause it had to be done in the work folder, this may have caused the issue.

i'm lost, can anyone help me?.

Altera_Forum · ‎09-13-2012

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Then you are not "listening" to what I am trying to explain to you. A Tcl script is just a series of commands.

You are using a Tcl script called PFC.tcl - where did it come from?

--- Quote End ---

I suppose was generated from files, if U go on on asking existence questions about tcl, then maybe i should ask for a better bibliography...

--- Quote Start ---

The Tcl script will do whatever you have written in it. If you have not written it to print messages, then of course it will not display anything in the console.

--- Quote End ---

Okay, what do this answer got to do with the modelsim compiling succesfull?

--- Quote Start ---

Don't take it that way. You are an "inexperienced" engineer. However, if you expect anyone to help you now and in the future, when you ask for advice, you need to listen to it, and then formulate follow-on questions indicating what you have done, and what you have failed to understand.

Cheers,

Dave

--- Quote End ---

Don't blame why young people don't study nowadays, sometimes i understand them, to get shattered this way.

Altera_Forum · ‎09-13-2012

To resume, after the prodigious sourcing of the code, this is the situation.

error (10481): vhdl use clause error at producten.vhd(3): design library "work" does not contain primary unit "fixed_package"

error (10800): vhdl error at producten.vhd(3): selected name in use clause is not an expanded name

error: quartus ii 32-bit analysis & synthesis was unsuccessful. 2 errors, 1 warning

Altera_Forum · ‎09-14-2012

Please if you are not gonna go directly to the whole mess, please connect more continously, or focus more.

Altera_Forum · ‎09-14-2012

Well, like you don't realise my situation and don't bother tell me a bad stdent, i will tell you that i cannot do the researching figure you would expect because i've got 10 days to endy my project if i fail, i will have to repeat the subject again, do you understand my hurries? Hope so.

And i've spent 3 days wandering without any advance, how do you think i would feel?

Altera_Forum · ‎09-14-2012

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don't bother tell me a bad stdent

--- Quote End ---

I'm not telling you you are a bad student. I am giving you advice on how to learn, regardless of whether you are a student or not.

Keep in mind that I do not work for Altera and do not have to help you. No one on this forum does. If you want help, then you have to have a good attitude in return.

I understand you are frustrated. The tools are complicated. You should have been given more time than 10 days to learn how to use a tool and to complete a project.

I can see that you are overwhelmed. Why don't you post your code and let me take a look. I'll try and setup a Quartus project for you that will work.

Cheers,

Dave

Altera_Forum · ‎09-14-2012

--- Quote Start ---

I'm not telling you you are a bad student. I am giving you advice on how to learn, regardless of whether you are a student or not.

Keep in mind that I do not work for Altera and do not have to help you. No one on this forum does. If you want help, then you have to have a good attitude in return.

I understand you are frustrated. The tools are complicated. You should have been given more time than 10 days to learn how to use a tool and to complete a project.

I can see that you are overwhelmed. Why don't you post your code and let me take a look. I'll try and setup a Quartus project for you that will work.

Cheers,

Dave

--- Quote End ---

Well,

1 I've been given a year, but the subject that teach me VHDL started on february.

2 The final exercise of the subject was to use I2C to start a D2 audio, i did never see I2C until this year, as a result to my poor skills, and thankfully i was helped by a colleage, i finished the 20 of july, on 30 of july my teacher who holds my project, went on holidays 30 days so he explained poorly my project by ovius reasons, so i didn't started (In summer i made the memory and all the teoric research) since 1 september, it has taken 12 days to wrote all codes in those 10 files you could see, nowadays i'm stuck in the modelsim that during the exercise didn't gave me any problems, i've asked my exercise master of the university and doesn't have any clue of Modelsim. So here we are.

Please help me as fast as you can, i go to a privete school since i am no good student for a public one and a single subjects costs lots of money to repeat it cause modelsim does not work.

Altera_Forum · ‎09-14-2012

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it has taken 12 days to wrote all codes in those 10 files you could see

--- Quote End ---

Please upload a zip file with the files, and I'll take a look.

--- Quote Start ---

Please help me as fast as you can

--- Quote End ---

Ok.

Cheers,

Dave

Altera_Forum · ‎09-14-2012

I should not post my code is my final 5th year engineering project by obvius reasons i can't.

Yes it is an easy project but i did not have more time for something bigger.

Altera_Forum · ‎09-14-2012

They can blame me on copiing if somebody advances me.

Altera_Forum · ‎09-14-2012

There is nothing you need to see, almost all files use:

in sfixed (1 downto -16);

so in the biggining they have:

use work.fixed_package.all;

Nothing more to see.

After the defense i can send you my code, if you want.

Well the original code had:

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

but we changed it.

Altera_Forum · ‎09-14-2012

--- Quote Start ---

I should not post my code is my final 5th year engineering project by obvius reasons i can't.

Yes it is an easy project but i did not have more time for something bigger.

--- Quote End ---

Ok, post an example design that generates the same warning message. For example, multiple two fixed-point numbers together and see if that gives you the error.

Alternatively, you can email me the files (my forum name is my email), and I will delete them once I we have synthesis and simulation working. This is not cheating, as I have no plans to help you fix your code. If there are errors in the code, I will provide hints on what to do.

Cheers,

Dave

Altera_Forum · ‎09-14-2012

--- Quote Start ---

There is nothing you need to see, almost all files use:

in sfixed (1 downto -16);

so in the biggining they have:

use work.fixed_package.all;

Nothing more to see.

After the defense i can send you my code, if you want.

Well the original code had:

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

but we changed it.

--- Quote End ---

Ok, I'll write you an example. I'll upload a zip file in a little while.

Cheers,

Dave

Altera_Forum · ‎09-14-2012

Don't bother, I sent my project to your mail (only the skeleton, there is no code even knowing the skeleton shows much...).

Consider i'm from spain (Europe), so these days I will go very late to sleep. Cause i see yo did not connect here until 5 pm here i cannot wait till 5 pm to progress tomorrow.

Altera_Forum · ‎09-14-2012

As you can see it's an easy project don't remember this to me... if anyone has 2 months for a project...

Altera_Forum · ‎09-14-2012

As promised, here is an example of how to setup Quartus to synthesize against the fixed-point package compiled into the ieee_proposed library, i.e., the original library files are not modified.


VHDL fixed-point package synthesis example
------------------------------------------
9/13/2012 D. W. Hawkins (dwh@ovro.caltech.edu)
This design shows a minimal example that uses the
IEEE proposed fixed-point packages.
During synthesis, there will be warnings in the Quartus message
window about the design not meeting timing. This is to be expected,
as there is no .SDC file included in this example. This design is
not meant to be downloaded into a device, its merely to show how 
to setup Quartus to use the fixed-point package library.
To synthesise the design:
1) Start Quartus
2) Make the Tcl console visible using
   View->Utility Windows->Tcl console
   
3) Change directory to the location of this example code,
   eg., if the zip file was unzipped into 
   c:\temp\vhdl_fixed_pkg_example, then at the Tcl console type
   cd {C:\temp\vhdl_fixed_pkg_example}
   The paranthesis {} allow the Windows path separator '\'
   to be used in the name, otherwise you need to use '/', i.e.,
   
   cd C:/temp/vhdl_fixed_pkg_example
4) Then source the file
    source scripts/synth.tcl
    The Tcl script will output its progress:
    Synthesizing the 'fixed_pkg_example' design
    -------------------------------------------
     - Quartus Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Full Version
     - Creating the Quartus work directory
       * C:/temp/vhdl_fixed_pkg_example/qwork
     - Create the project 'fixed_pkg_example'
       * create a new fixed_pkg_example project
     - Creating the VHDL files list
     - Applying constraints
     - Processing the design
     - Processing completed
   The synth.tcl script has configured a Quartus project. After this
   point, you can edit files (eg. change parameters in fixed_pkg_example)
   and press play on the GUI to re-synthesize the design.
   
5) In the Quartus GUI, on the left-side is the "Project Navigator"
   window. The "Hierarchy" tab will be selected.
   
a) The "Hierarchy" window has a slider bar along the bottom.
   Slide it and you will see that this simple design requires
   a single DSP Block in the Cyclone IV E device.
b) Click on the "Files" tab. There will be four files listed:
   
   fixed_float_types_c.vhd
   fixed_pkg_c.vhd
   sfixed_multiply.vhd
   fixed_pkg_example.vhd
   
   These files are listed in the order they are compiled. The
   packages need to be compiled before any files that use them.
   
   Select the fixed_float_types_c.vhd file, right-click, and
   select "Properties". Note that the "Library" field is
   ieee_proposed. This is the VHDL library that the 
   fixed_pkg_c.vhd code expects to find type definitions,
   i.e., at the top of the file fixed_pkg_c.vhd is the lines
   
   library IEEE_PROPOSED;
   use IEEE_PROPOSED.fixed_float_types.all;

Cheers,

Dave

Altera_Forum · ‎09-14-2012

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I sent my project to your mail

--- Quote End ---

Please do the following;

1) Start Quartus and open your project

2) Click on the "Project Navigator" "Files" tab.

Note that the packages are not at the top. You need to move them first in the compilation order.

Even if Quartus can handle the packages out of order, if you use Quartus to automatically generate a simulation script for Modelsim, you will want the Modelsim script to have the package files first.

3) Click on the menu option "Project->Add/Remove Files from Project"

You'll see the files in the order seen in the attached JPG.

Highlight the package files by clicking on them, and the use the "Up" button to move them up in the compilation order.

Make sure all of the packages your design uses are listed in the GUI. If there are files missing, you will get synthesis errors.

If you want to use the fixed-point packages in their original form (without edits) take a look at the screen shot I just added to the example design above. Note how there is a library name next to those VHDL files.

Cheers,

Dave

Altera_Forum · ‎09-14-2012

Hello,

No changes, if i chose to call all

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

for:

use work.fixed_package.all;

this modelsim error:

# ** error: fixed_pkg_c.vhdl(22): library ieee_proposed not found.# ** error: fixed_pkg_c.vhdl(23): (vcom-1136) unknown identifier "ieee_proposed".# ** error: fixed_pkg_c.vhdl(28): vhdl compiler exiting# e:/altera/11.1sp2/modelsim_ase/win32aloem/vcom failed.

or this quartus error:

error (10481): vhdl use clause error at pack.vhd(9): design library "work" does not contain primary unit "fixed_package"

error (10800): vhdl error at pack.vhd(9): selected name in use clause is not an expanded name

you can choose the fun.

Alfonso.

PS: I think you talked to me to use some libs for some files. Except the main, and the uart, all other need sfixes. You suggest me to use

use work.fixed_package.all; only for main and uart, will it work?

Altera_Forum · ‎09-14-2012

Hi Alfonso,

You need to focus on one problem at a time.

Ignore Modelsim for now, and get Quartus working first.

1) Start with the example design I gave you.

2) Run the script.

This will get you a Quartus project where the libraries are setup correctly.

3) Add your files to the project.

Edit them to have:

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

since the project now has the libraries configured correctly.

4) In the "Project Navigator" "Files" window, right-click on your top-level file and click on "Set as top-level entity".

The project name will still be fixed_pkg_example, however, it will now compile your code for the top-level project.

At time point you should be able to compile your code without any errors related to libraries. If you see errors, then read the messages, and look in the files that are generating the errors. Make sure you have the library statements in step (3).

Cheers,

Dave

Altera_Forum · ‎09-14-2012

--- Quote Start ---

Hi Alfonso,

You need to focus on one problem at a time.

Ignore Modelsim for now, and get Quartus working first.

1) Start with the example design I gave you.

2) Run the script.

This will get you a Quartus project where the libraries are setup correctly.

--- Quote End ---

http://i46.tinypic.com/21e57gl.jpg

False nothing happens:

--- Quote Start ---

3) Add your files to the project.

Edit them to have:

library ieee_proposed;

use ieee_proposed.fixed_pkg.all;

since the project now has the libraries configured correctly.

4) In the "Project Navigator" "Files" window, right-click on your top-level file and click on "Set as top-level entity".

The project name will still be fixed_pkg_example, however, it will now compile your code for the top-level project.

At time point you should be able to compile your code without any errors related to libraries. If you see errors, then read the messages, and look in the files that are generating the errors. Make sure you have the library statements in step (3).

Cheers,

Dave

--- Quote End ---

Altera_Forum · ‎09-14-2012

Forget what we said, i've read on the datasheet i miss the library:

use work.FIXED_PKG.ALL

with it, the quartus works

but we are stuck at modelsim:

# ** Error: C:/Users/Alfonso/Desktop/PFC/fixed_pkg_c.vhdl(22): Library ieee_proposed not found.# ** Error: C:/Users/Alfonso/Desktop/PFC/fixed_pkg_c.vhdl(23): (vcom-1136) Unknown identifier "IEEE_PROPOSED".# ** Error: C:/Users/Alfonso/Desktop/PFC/fixed_pkg_c.vhdl(28): VHDL Compiler exiting

Repeat it to me over WHICH LIBRARY MUST I COMPILE, over work or over rtl_work

So:

vsim> vlib rtl_work

vsim> vmap rtl_work [pwd]/rtl_work

vsim> vcom -work rtl_work <your VHDL files>

or

vsim> vlib work

vsim> vmap work [pwd]/work

vsim> vcom -work work <your VHDL files>

Altera_Forum · ‎09-14-2012

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False nothing happens:

--- Quote End ---

Sorry, when I edited my readme.txt, I dropped the line that ran the script.

I've edited the previous posting with the code to show that after changing directory you must run (source) the script.

Cheers,

Dave