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This may be a stupid question :confused: but I'm having a hard time with it. every time I think I get it I get confused again. can someone please explaing this? what happens with lets say a simple counter if it has a count enable, or a clock enable?
help! I'm trying to create a pulse with the FPGA starter kit, but i want an outside signal to control whether the pulse will be created or not.Link Copied
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Clock enable affects all synchronous activities (sload, sset, or sclr.) and stops counting.
Count Enable stops the counter from counting. You are still able to use sload, sset, or sclr.- Mark as New
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Thank you!
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