Custom IP in Qsys

[Altera_Forum]

Hi All, 

 Maybe some of you might be familiar with my problem with Qsys.  I'm trying to add a custom IP to a SoCKit lab project that will be accessible via the JTAG Avalon Master.  Since my custom IP will have an Avalon MM slave interface, i tried creating a BLANK component in Qsys that has a clock, reset, and an Avalon Memory Mapped Slave interface. My plan is to then use this blank component as a placeholder to add in my custom logic. (Please advise if you think there's a better approach)  I've added the avalon_slave signals that my custom IP will use (read, readdatavalid, waitrequest, etc...). Set the widths accordingly. Then added it to the SoCKit HW lab design.  When i've added my custom IP to the SoCKit Qsys project, i then connect my custom IP to a JTAG to Avalon Master Bridge. I then set the Base address accordingly. Then worked on the Quartus project to add in my custom IP files. Compiled the design and program it in my SoCKit.  Where i get confused is how does Qsys compute the END address? My custom IP has  - 32bit address width  - 64 bit data width (both for read databus and write write data bus)  - I've set the Address Units to Symbols, Bits per symbol to 8, Burst Count units to Words, and Explicit address Span to 0x8000  With the above setting, Qsys has my end address to 0x012b.... i can't figure out how that came out.   When i set the Explicit Address Span to 0x4, i get an end address of 0x0003, but when i set the Explicit Address Span to 0x8000, i get 0x12b??   I am seeing a lot more issues when i try to test my custom IP on hardware but I think the issue i've stated above might be the main cause. An example problem i'm seeing on hardware is that in order for me to access a test register at address 0x0002_0200, i need to do a master_write_8 $jtag_master to address 0x0004_0200! When i do that, i can see the avalon address bus set to 0x0002_0200. If i use the actual address, i see (from signaltap) 0x0000_0200 on the avalon address bus!  Thanks!  PS I tried posting this to altera tech support but it appears to be down again. It's been acting up for me since last week. Transferring me to the chinese version.

[Altera_Forum]

Question: are you using any pipeline bridges?  

 You should create the qsys component at the end of the design and add your files at the same time. Add the simulation files as well so you can create a testbench of the system. I usually dont change the default Explicit Address Span and usually works fine. What i do see what is important is having the correct timing diagram for each signal. I have ran into a lot of timing problems because i have overlooked them. The test bench will show you some of these issues. Also you can add a nios system into the design if your having problems seeing the address. When you create a nios system in eclipse the system.h has the addresses stored. you can use nios for testing as well. Hope it helps :)  -Trukng

[Altera_Forum]

Hi Trukng, 

 I'm not using any pipeline bridges.  I've managed to make it work and what "did" it, i think, is when i also tapped the HPS' h2f_lw_axi_master bus to my custom IP. I was only tapping it to the JTAG to Avalon Master bridge. I'm now seeing it at the correct address and i can do the jtag read/writes OK.  Thanks!