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Altera_Forum
Honored Contributor I
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CvP Programming

I'm having an issue with programming a board through PCIe. I've been following the CvP Driver Flow document and the issue I run into is that in the 'Teardown' part of the process the CVP_CONFG_READY bit is always set to 1. The bit will does not change and I am unaware of how to change it. If I were to skip over the condition the same issue happens with the PLD_CLK_IN_USE and the USER_MODE bits. Both are set to 0 and does not ever appear to change. Any assistance would be greatly appreciated.

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