Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

CyclonIII PDN

Altera_Forum
Honored Contributor II
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I'm new to the CycloneIII device, and I'm working on a board that uses the CycloneIII. I have no particular Altera design that will live in the Cyclone, as it is a general purpose board, so the Cyclone design could be anything. Without a specific design, I have no way of estimating the chip's power demands, correct? Has anyone out there built a board like this? I am interested in what you implemented for your power distribution network, in particular, what regulator chips you used, and how you chose the decoupling capacitor values. 

 

Thanks, 

Andy
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Altera_Forum
Honored Contributor II
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thanks a lot:D

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Altera_Forum
Honored Contributor II
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i am also new to altera. i am using CYCLONE III . i am stuck at qsys. my design is pretty simple. its like this  

 

Nios II processor -encoder - avelon bus- decoder- memory.  

 

the encoder and decoder are VHDL codes that i am using . i am in need of hel[p about how to interface and connect the system using qsys.
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