We are searching for an FPGA that is economical in terms of power.
In the past we have seen, that many devices share a common die and only restrict the resources artificially. When looking at static power you "pay" for all that is present and together with high temperatures this gets ugly fast.
There is a gap in the Cyclone 10 GX overview between the 85er device and the rest in respect to the number of transceivers etc. so we hoped, that it might be a separate, optimized device (in the same way as Xilinx has just presented the ZU1 to address the lower ranges).
The early power estimator (Excel sheet) won't change the static power when you switch the devices but I still hoped for ... ES chips that were done the same die at the start?
It might be that all this information is somewhere available - in that case please excuse my unnecessary questions. It is however a crucial question at the very start of a project
=> Would be nice to be sure
Sorry for the late response.
If you are looking for the low static power devices then Cyclone 10 LP family is actually meant for that. As I am not aware of your design requirement, hence can't recommend any particular device. You may check the device overviews for that.
For the power estimation sheet, yes the static power is fixed. You can still have a fairly close estimation if you enter correct design and environment details in the sheet.
we already use the Cyclone IV E (which is very similar to the 10LP) in some of our products.
We definitely need some transceivers - 5/6.x GBit would be the minimum, 10GBit would be nice.
=> At this point, the Cyclone 10 GX seems like an almost perfect fit - Cyclone V GT
would be "okay" but is a little bit outdated.
If the static power of 10CX085 <-> 10CX220 is the same due to a shared hardware it is
very unfortunate for us - but thanks for clearing it up.