Cyclone 10 LP LVDS capability

[davekrzy]

Can cyclone 10 work with a 250MHz DDR input?  LVDS common is 1.25V, differential is 200mV and clock rate is 250 MHz.  Thanks.

[FvM]

Hi,
general answer is yes, Cyclone 10 LP can achieve at least 640 MBPS LVDS data rate (with slowest speed grade), review datasheet.

The question is however no very clear, are you referring to data rate or DDR clock. It's also important to know how the receive clock is provided, e.g. sent to the FPGA along with the data? Extracting clock from received data (CDR) isn't natively supported by Cyclone 10 LP FPGA family.

[AqidAyman_Intel]

Hello,

You can refer to the datasheet here on the LVDS specification of Cyclone 10 LP:

https://www.intel.com/content/www/us/en/docs/programmable/683251/current/differential-i-o-standard-specifications.html

LVDS Receiver Timing Specification:

https://www.intel.com/content/www/us/en/docs/programmable/683251/current/lvds-receiver-timing-specifications.html

Regards,

Aqid