I have been following AN661 and how to video: https://www.altera.com/content/dam/altera-www/global/en_us/video/e2e/pll-reconfiguration-with-mif-fi... to understand how the PLL reconfiguration can be implemented. i am targeting Cyclone 10 LP - 10CL025 part and using Quartus Prime Lite 17.1 tools. i know that the application note and video are targetting older parts, i was told by the support person to use these as reference to target this new FPGA. 'ALTPLL' and 'ALTPLL_RECONFIG' IPs i see in the tool show different inputs enabled when selecting the reconfiguration option in the PLL wizard than it is shown in the video and AN661.Attached 'allpll.jpg' and 'pll_reconfig.jpg' are what i see in the tool. But the above video (snippet attached 'video_setup.jpg' ) show different inputs enabled for PLL and pll_reconfig for PLL reconfiguration application. Questions: - How do I get to ‘Altera IOPLL’ IP option as shown in the video for cyclone 10LP part ? - Enabling the dynamic reconfiguration, gives me the scanxxx signals? How do I get to the IP configuration as shown in the video and AN661 example designs? - Is there any tutorial or app note with step by step instructions for PLL reconfiguration for Cyclone 10LP part? Thank you very much!
The video is using Platform Designer (aka Qsys) to connect ALTPLL_RECONFIG to the PLL. This is the easiest way to do it. You can, of course, just connect through RTL coding as well. Have you read through the ALTPLL_RECONFIG IP user guide?https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altpll_reconfig.pdf