Cyclone 10 LP configuration/JTAG pin VCCIO

[yes2]

Hi, I am designing a PCB that uses a Cyclone 10 LP. Due to PCB space constraints, I was planning on leaving 2 IO banks on the FPGA unconnected to VCCIO (or at least without any decoupling capacitors).

One of the banks I'm not using contains the programming configuration pins (INIT_DONE etc), are these I/O's powered through the VCCIO of the relevant bank? In which case I would have to connect the VCCIO of the bank (but can likely get away with using very little decoupling capacitors due to low switching speed).

Thank you!

[FvM]

Please refer to user manual
"The POR circuit of the Intel Cyclone 10 LP device monitors the VCCINT, VCCA, and VCCIO (of banks 1, 5, 6, and that contain configuration pins during power-on. You can power up or power down the VCCINT, VCCA, and VCCIO pins in any sequence. The VCCINT, VCCA, and VCCIO must have a monotonic rise to their steady state levels. All VCCA pins must be powered to 2.5V (even when phase-locked loops [PLLs] are not used), and must be powered up and powered down at the same time."

[yes2]

Thank you.

[Fakhrul]

Hi yes2,

I wish to follow up with you on this case. Do you still have further inquiries on this issue? Please feel free to let me know if there is any concern so that we could further assist you.

Regards,

Fakhrul

[Fakhrul]

As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Intel experts. Otherwise, community users will continue to assist you here. Thank you.