Cyclone 10LP 1.8V specifications

[ivar_svendsen]

Hello,

I am reviewing a design for digital IO compatibility.

The Cyclone 10LP Datasheet specify VOH=VCCIO-0.45V and VOL=0.45V at 2 mA. This seem incompatible with some 1.8V devices that require 20% for VIL (0.36V).

EDIT: Reading further, the Core Fabric handbook claims JEDEC8-7 compliance, and names both 1.8V LVTTL and LVCMOS. I guess the Cyclone 10LP may successfully those other chips, provided the current drawn is less than 100 uA (limit according to JESD8-7A).

Regards,

Ivar Svendsen.

[AqidAyman_Intel]

Hello Ivar,

May I know what is your main concern on the datasheet of 1.8V I/O standard specification?

[AqidAyman_Intel]

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[ivar_svendsen]

After a long time, I am able to follow up on this topic.

I will try to rephrase my question:

At 1.8V, the IO has JEDEC8-7 compliance.

JESD8-7A output is 0.45V (low) and VDD-0.45V (high).

However, I have found several other logic circuits claiming to be "1.8V LVCMOS" or "1.8V LVTTL" compatible, with stricter IO thresholds.
This other logic require 0.3V (low) and 0.8*VDD = VDD-0.36V (high).

The question is what spec is that other logic, and is it actually compatible with the Cyclone 10LP (JESD8-7)?

Ivar Svendsen.