I am using Cyclone 10LP to catch data from AD9257. Data and frame clock coming form ADC are LVDS signals and frame clock is connected on clock capable LVDS pins.
Frame clock is forwarded to PLL to generate fast clock. ADC data are connected to DDIOs running on this generated fast clock
Problem is extra latency of one clock that I have and I don’t know where does it comes from. On image below you can see frame clock, input data and generated fast clock. Now I would expect a case 1 where DDIO data is delayed for one fast clock regarding to frame clock but I have a second case with 2 clocks delay.
Does someone know what causes this extra clock delay?
thank You very much for engagement.
Problem is meanwhile solved; it was a stupid copy paste mistake where I looked the data on the output of a register that comes after DDIO and that caused this one extra clock latency.
P.S. I was a little ashamed, so I didn't write in the forum that the problem was solved, but I will do that next time.