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Altera_Forum
Honored Contributor I
1,034 Views

Cyclone 10LP and Cyclone 10GX - Are they really new?

Dear all, 

 

I had planned to use 10LP in my newest designs but after going through some online discussions I saw that 10LP is 60nm nothing but, Cyclone III essentially renamed. Similarly, 10GX is Arria 10 lower end devices renamed. Is it true that these are just in response to Xilinx's announcement of cost optimized portfolio? I'm a big Altera fan and and wish these are just rumors. But the 10LP overview page also says 60nm. Nothing wrong in re-branding the chips, but just want to know because I'm torn between MAX10 and 10LP for my next board, not sure which one to use, onchip flash is not a must for me.. at the same time I like the price point of 10LP. 

 

Inchara
0 Kudos
3 Replies
Altera_Forum
Honored Contributor I
49 Views

Hi, 

 

Yes its is new. 

Cyclone III is 65 nm process and Cyclone 10Lp is 60 nm process. 

Max 10 is 55 nm process. 

https://www.altera.com/en_us/pdfs/literature/sg/product-catalog.pdf 

https://www.altera.com/products/fpga/cyclone-series/cyclone-iii/features/cy3-65nm-lowpower.html 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
49 Views

Thanks. The catalog says 60nm and the webpage says 65nm - less important to worry about the discrepancy.  

 

Whether it is 60nm or 65nm, still do not understand how 50% power reduction is claimed compared to the 28nm Cyclone V in the picture on page 2 of the catalog. Also I do not understand MAX10 offering 50% board size reduction especially the user flash being very small in size and the boot segment can be replaced by a QSPI chip which is < 3mmx3mm.  

 

On a related note, is Cyclone 10 SoC in pipeline?
Altera_Forum
Honored Contributor I
49 Views

Hi, 

 

1. Process of cyclone III and Cyclone 10 LP there is conflict in the documents below for cyclone III one documents tell it is 60nm and other it is 65nm process? 

The statement for the Cyclone III build with 60nm is still true. I guess the catalog just lump the 65nm together under as 60nm category. You can check the information from the each FPGA device Configuration handbook chapter.  

Cyclone 10 LP devices are manufactured using the TSMC 60-nm low-k dielectric process. 

Cyclone IV devices are manufactured using the TSMC 60-nm low-k dielectric process. 

Cyclone III devices are manufactured using the TSMC 65-nm low-k dielectric process.  

Cyclone III LS devices are manufactured using the TSMC 60-nm low-k dielectric process. 

 

2. how 50% power reduction of Cyclone 10 LP is claimed compared to the 28nm Cyclone V? 

I believe the statement here focus on the lower power static being offer in Cyclone 10 LP. We have reduced the power of Cyclone 10 LP, compared to previous generations of Cyclone, by tuning the fab process to be more aggressive for meeting lower static power. The benchmark comparison among Cyclone family device was done which in result for among the non-transceiver Cyclone series devices, Cyclone 10 LP leads with the lowest cost and power. 

 

3.Is there Cyclone 10 SoC in pipeline? 

There are no plans for an SoC variant. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)