Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20704 Discussions

Cyclone 3 - configure M9K in 8-bit mode?

Altera_Forum
Honored Contributor II
‎10-28-2015 07:51 PM
936 Views

Hello, probably question which was asked not once before, but I can not find instant answer. 

 

I have 32KBytes of the RAM configured using M9K blocks, 8 bit data bus width. If I configure it by default, I lose 9th bit off the each address location, which is 32768 bits = 4KBytes. Can I somehow internally to the device configure it to use its RAM array organized x8 bus width? 

 

I gave a thought doing it "externally" in the configuration, but it is too much timing and processing overhead. 

 

Please advise.
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎10-30-2015 10:09 AM
244 Views

No, if you really need to use all the bits you will need to add an external module to map them, but as you say it will probably induce a timing overhead.

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.