Programmable Devices

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Programmable Devices

Discussions

modified dma, pcie sopc example does not allow reads after first dma write

Problem with NIOSII IDE

.pof to cfi flash S29GL512N

Clock Skew Issue

Protecting EPCS

Fast clock speed remote_update

PLL problem after power on reset

Building a Transfer Function using Simulink/DSPBuilder

Apex/Cyclone III I/O compatibility

Can the TX of Transceiver-A be routed to the RX of Transceiver-A ext to the FPGA?

Can the TX of Transceiver-A be routed to the RX of Transceiver-B internal to the FPGA

DCFIFO read/write request control

Implementing an accumulator and data recovery system

Getting to grips with Quartus II

DMA controller in SOP buidler question

Featured Content

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

EPM3064ATC44-7N and EPM3064ATI44-10N

Deserializers in Agilex 3 series

Re: Download speed

Re: Quartus Prime Design Software - JTAG usage