Cyclone 4 GX - Transceiver - EPCS-pins cannot be used?

[Altera_Forum]

Hi, 

 we have a prototype board where we want to use REFCLK4 (Pin L10, F27-package) as reference-clock for a transciever. Now it turned out that we cannot access the EPCS-pins anymore when we use a data-rate of 2.97Gb/s (which we require).  Is there any way to make Quartus allow the usage of the EPCS pins, so that we can make at least some tests with our prototype-boards?  Thanks in advance,  Thomas

[Altera_Forum]

Try putting the toggle rate on those signals to zero 

 http://www.altera.com/support/kdb/solutions/rd05052003_3407.html  The Tcl constraint is  set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to $port  where $port is the name of an EPCS pin.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 thank you for your suggestion. We knew this trick already and tried it, but it did not work. I think it only works for regular LVDS-pins, not for transceivers. (I have the design not here in the moment, so I cannot double-check again. We are using QII 11.1sp2, maybe another version would do?)  Regards,  Thomas

[Altera_Forum]

How are you interfacing to the EPCS pins? 

 Have you tried specifying them as "Use as regular I/O", and then setting the toggle constraint?  Cheers, Dave

[Altera_Forum]

Yes, this is the way we did it. 

 The only way we can get the design compiled is by setting the respective 3 configuration-pins to "Compiler configured". (DCLK is not restricted, only MISO/MOSI/CS.)  Thanks,  Thomas

[Altera_Forum]

File a Service Request directly with Altera and see if they have a suggestion. 

 If they do come up with something that works, please post the solution here for others to see.  Cheers, Dave