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Honored Contributor I
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Cyclone 4 with DDR memory interface?

Hi. Having used FPGA's since the dark ages, I am making a decision to use either the Cyclone 4 or the Cyclone 3 with a NIOS II processor core. This is NOT a NIOS question.  

 

I have been reading the "External Memory Interface Handbook" and have learned that the Cyclone 4 does not have OCT (On Chip Termination) with respect to parallel termination, as does the Cyclone 3 and Stratix families (page 1-4 table 1-1) . I am wondering if this is a potential drawback. This leave me with only the option of using external "fly by" termination, that can use a lot of board real estate. 

 

Does anyone know the reason why Altera removed OCT from the Cyclone 4 family of devices?  

 

Is the cyclone 3 family better for interfacing to fast external memory devices? 

 

Thank You 

Tom
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Honored Contributor I
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There are plenty of references to OCT in the Cyclone IV handbook. This includes sections specifically about external memory interfaces. For example, in one spot the handbook states, "This section discusses Cyclone IV memory interfaces, including DDR input registers, DDR output registers, OCT, and phase-lock loops (PLLs)." 

 

My experience has been that Cyclone IV is very similar in features to Cyclone III. This is especially true when comparing Cyclone III to Cyclone IV E in which case the parts seem to be virtually identical. The Cyclone IV GX adds the significant feature of the high speed transceivers.
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Honored Contributor I
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As kevin says there is no parallel OCT in Cyclone III either. 

Depending on your set-up you can look into using series termination. E.g. If you only have one DDR2 device you can use OCT series termination not only for the address and command lines, but also for the DQ and DQS lines coupled with additional series termination resistors at the DDR2 device's side. This gives you the minimum amount of external terminating resistors. You have to disable ODT in the DDR2 controller. And you have to account for the extra rise time (== additional delay) in the timing constraints.
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Honored Contributor I
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Thank you for the informative responses to my post. 

 

joseyb, I do have issue with the first statement of your response.  

 

"As kevin says there is no parallel OCT in Cyclone III either." 

 

I have attached table 1.1 from the "external memory interface handbook" and it implies that the Cyclone 3 does have internal parallel OCT. Also, I re-read Kevins post and I don't see where he says that there is no parallel OCT in Cyclone 3. Can you tell me what it is that I am not seeing? 

 

Thank You 

Tom
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Honored Contributor I
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doesn't the table imply that CIII and CIV do not have parallel OCT?

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Honored Contributor I
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joseyb, I might have found part of the answer but it is still confusing. Attached is a statement from page 119 of the external interfaces manual. It does say that neither Cyclone 3 or Cyclone 4 use OCT but it implies that it is the Altera IP that does not use OCT. This seems to conflict with table 1.1. Not sure how to interpret this. 

 

Tom
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Honored Contributor I
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You are quite correct! Evidently I can not read early in the morning. I mistook the label Stratix III for Cyclone III. This clears things up.  

 

My thanks to all who responded.
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