Cyclone 5 SE SoC FPGA Hard DDR3 MEMORY INTERFACE - timing closure

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Cyclone 5 SE SoC FPGA Hard DDR3 MEMORY INTERFACE - timing closure

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Hi,

I've instantiated the hard DDR3 memory controller in my design for use by the FPGA fabric but I'm getting errors reported by TimeQuest about recovery and removal on the reset lines.

I'm tried driving the global and soft reset inputs from registers synchronised to the user clock & pll_write clocks, both options cured some faults but not all of them.

I've tried locking the placement of the reset driver FFs close to the hard memory interface block, if anything this made it worse.

Has anyone found a way to meet timing?

Is it safe to ignore these faults (looks like one of the circuits the reset goes to is a counter so probably not ok to ignore it?)

I'm running it at 367MHz with a 150MHz user clock from a 50MHz ref input clock.

Speed grade 6 with Commercial temp range.

Dan.

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