i'm currently designing a board with a Cyclone V SE with a single 16 bit DDR3 connected to Bytelanes 0 and 1.
in order to simplify the layout, the layouter requests to use other bytelanes instead. since i can't find any info on this in the datasheets i'm requesting it here.
For instance DQ0-7 on bytelane 1 and DQ8-15 on bytelane 4, is this supported in HW?
Is the bytelane that you saying here referring to HPS_DQS_0 and HPS_DQS_3 in the pin-out file?
If yes, you suppose can place the DQ pin into these groups as they are HPS DQ pin. Anyway, after you place it, try to fit with quartus full compilation to confirm.
thanks for your reply,
Currently DDR DQ0-7 nets ('bytelane 0') is referring to HPS_DQS_0 and HPS_DQS#_0 (Pins R17/R16) and DDR DQ8-15 nets ('bytelane 1')is referring to HPS_DQS_1 and HPS_DQS#_1 (Pins R19/R18)
The layouter requests to connect DDR DQ0-7 nets ('bytelane 0') is referring to HPS_DQS_1 and HPS_DQS#_1 (Pins R19/R18) and and DDR DQ8-15 nets ('bytelane 1')is referring to HPS_DQS_4 and HPS_DQS#_4 (Pins V18/V17)
i'll ask the quartus colleague to check this in the tooling
Yes, it should be ok as you can use any available DQ/DQS group (byte) from the FPGA to build your x16 interface.
Anyway, as mentioned please try to fit it in Quartus. If quartus does not complaint then it is good to go. 😉