How to assign pin as a clock?

[KVane4]

I have been using MAXII and MAXV CPLDs for some time, but have just started transferring to a MAX10 FPGA. I have started with some simple logic to generate clock signals and I get project compiles with numerous warnings about the pin that I am using for the clock input. I am using 10M08SCU169A7G FPGA with a 30Mhz oscillator connected to ball H6 (CLK0p). This pin is the clock input to an ALTPLL block. Although the project builds and runs correctly, I get the following warnings:

"Node: CLK0p was determined to be a clock but was found without an associated clock assignment"

"The master clock for this clock assignment could not be derived. Clock: inst|altpll_component|auto_generated|pll1|clk[0] was not created."

"Virtual clock CLK0p is never referenced in any input or output delay assignment".

There are numerous other warnings about no clocks defined.

I also want to assign the output of the PLL as a global clock and the fitter is ignoring that assignment.

Although when I load the project it seems to be functioning correctly, it certainly seems as though I am doing something wrong. It also seems that the timing analysis is not working because "inconsistent clock settings".

I have searched the forums and followed the sample projects and I can't find any information on this.

How do I correct these warnings?

[sstrell · Accepted solution]

It sounds like you have not created a timing constraints file (.sdc) for the design. Once your clocks and I/O delays are constrained, you won't get those warnings anymore. To learn about SDC and creating timing constraints, start here:

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html

#iwork4intel

[KVane4]

I did have an .sdc file but the clock was not properly defined. I fixed that and the warnings went away.

Thank you for your help.

[AnandRaj_S_Intel]

Really appreciate Kevin,

Thanks for sharing the solution.