Cyclone 5 fpga is not booting from spi flash

[Altera_Forum]

Hi all, I am trying to boot cyclone 5 (5cgtfd7d5f27i7n) FPGA from QSPI FLASH (epcq128si16n) .I am doing following steps: 1. I compiled counter program for blinking LED in quartux2,assigned FPGA pins, generated.sof file, downloaded it in to FPGA its working. 2. I converted .sof file to .jic file for flash and loaded in to flash. I referred the document given below. https://www.altera.com/en_us/pdfs/literature/an/an370.pdf. 3. In programming window, flash programmed successfully message appear. Info (209060): started programmer operation at fri jan 05 16:19:14 2018 info (209016): configuring device index 1 info (209017): device 1 contains jtag id code 0x02b030dd info (209007): configuration succeeded -- 1 device(s) configured info (209018): device 1 silicon id is 0x18 info (209044): erasing asp configuration device(s) info (209023): programming device(s) info (209011): successfully performed operation(s) info (209061): ended programmer operation at fri jan 05 16:20:40 2018 4. After that power off the board and again power on than FPGA not booting from flash. 5. Than first we checked power sequencing of power supplies and it found ok .Tramp is 20 millisecond as we observed on oscilloscope . 6. After power on we monitor nconfigpin, status, config done pin before FPGA programming. FPGA_nCONFIG = HIGH FPGA_CONFIG_DONE=LOW FPGA_nstatus = toggling FPGA_nCSO = HIGH 7. After FPGA configuration with.sof file FPGA_nCONFIG = HIGH FPGA_CONFIG_DONE=HIGH FPGA_nstatus = HIGH FPGA_nCSO = HIGH 8. After programing flash FPGA_nCONFIG = HIGH FPGA_CONFIG_DONE=HIGH FPGA_nstatus = HIGH FPGA_nCSO = toggling FPGA_DATA PIN = HIGH During flash programming: DCLK toggling (10 MHz observed in oscilloscope). BUT still FPGA not booting from SPI FLASH. Anybody has any idea if Cyclone V FPGA booting from the QSPI or not ? If booting from QSPI than wt is mistake in my above process? Any other thought or suggestions that can help understand the problem will be highly appreciated. Thanks & Regards DEEPAK KUMAR

[Altera_Forum]

How are your MSEL pins set? 

 What rate is nSTATUS toggling? It should only ever follow nCONFIG. Any other activity on nSTATUS indicates the FPGA has detected an error in the configuration stream. Refer to the "AS Configuration Timing Waveform", figure 7-4 in the "cyclone v device handbook (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf)".  Cheers, Alex

[Altera_Forum]

Hi 

  MSEL PIN [4..0] =10011  After loading the .jic file or .sof nstatus is high and ncso pin toggling.  Thanks   Deepak kumar

[Altera_Forum]

I've just re-read your original post. You've stated that CONF_DONE (FPGA_CONFIG_DONE?) does go HIGH after booting from FLASH. Is that right? If this is the case the FPGA has booted successfully. 

 So, I assume it doesn't behave as it does when you program it with the sof via JTAG. If this is the case I'd question whether the FPGA rails are powering up correctly. You can delay the start of AS configuration by holding nCONFIG low. Try this to delay configuration and give the rails longer to come up and settle.  Cheers, Alex

[Altera_Forum]

You've stated that CONF_DONE (FPGA_CONFIG_DONE?) does go HIGH after booting from FLASH. Is that right? If this is the case the FPGA has booted successfully. 

 CONF_DONE (FPGA_CONFIG_DONE) going high after i programmed flash.Again if i power off and on than (FPGA_CONFIG_DONE) not going high ,it is low and nstaus is also toggling.   Thanks & Regards DEEPAK

[Altera_Forum]

CONF_DONE high after programming the FLASH is because the FPGA is configured with the FLASH loader image used in jic programming. 

 Monitor nSTATUS during configuration from FLASH and look for an error. If all is well it should only ever follow nCONFIG (which I suspect you have pulled up). So, neither nCONFIG nor nSTATUS should do anything. nSTATUS going low will indicate an error.  Confirm you've generated the .jic with the right .sof.  Finally, as previously suggested, hold nCONFIG low to delay configuration.  Cheers, Alex