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Altera_Forum
Honored Contributor I
941 Views

Cyclone 5 maximum size DDR3

For Cyclone 5 FPGAs, what is the maximum size of the DDR3 memory in GB that can be connected to the FPGA hard memory controller and the HPS memory controller? 

I took a fast look on the datasheet but could not find the answer.
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3 Replies
Altera_Forum
Honored Contributor I
63 Views

Hi, 

 

according to the handbook "cyclone v devices support up to two hard memory controllers for ddr3, ddr2, and lpddr2 sdram devices. each controller supports 8 to 32 bit components of up to 4 gigabits (gb) in density with two chip selects and optional ecc. for the cyclone v soc devices, an additional hard memory controller in the hps supports ddr3, ddr2, and lpddr2 sdram devices." (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_51001.pdf#page=26

 

Cheers, 

fade
Altera_Forum
Honored Contributor I
63 Views

In most eval kits I saw ( I also tried designing my board) I found that they use 1GB DDR3 (two chips each 4Gbits and each is 16-bit width) and once chip select is used. The chip select 0 of the Cyclone 5 SOC is connected to the two DDR3 chips. 

Does this mean I can use 2GB DDR3 for the FPGA or the SOC?
Altera_Forum
Honored Contributor I
63 Views

Maximum size will be determined by the specific Cyclone V device you chose, the IP and the number of instances of that IP you're allowed/able to fit in the device. I suggest you play around with the IP configuration tool for the device you're interested in. 

 

Cheers, 

Alex
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