I've implemented fractional pll reconfig successfully as described here:
https://www.altera.com/en_US/pdfs/literature/an/an661.pdf Its working great. I found the instructions for the Cyclone V fPll much simpler to follow than on older devices.
However it takes a lot of logic elements! The mif streaming was enormous so barely fit in the FPGA. However even without that its about 1000 ALMs per instance. So to reconfigure two plls on a 5CEBA2F23C8 takes about 20% of the FPGA!
Does it work to share one instances and switch reconfig_to_pll with a mux? Or does anyone know the protocol of reconfig_to_pll so I could implement my own reconfig logic?
