Hello all,
In the "clock management" section of the Cyclone-I handbook, I see that the clock input to the PLL can be either single-ended or double-ended (LVDS). I see a multiplexer at the clock input of the PLL. Is it the case that, if two single-ended clocks are being used, then this multiplexer can be used for selecting between these two clocks. I don't see this mentioned in the handbook. Can someone please confirm that this is not the case for Cyclone-I FPGAs.
If this possibility exists, then we can use just one PLL for two different cystals, rather than two PLLs.
regards,
rajesh
