Programmable Devices

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.

Programmable Devices

Discussions

Connecting Digital Signal to De1-SoC

Black Box QSYS Components

Thunderbolt (PCIe) on FPGA

How to rum QCMD from cmd window for different quartus version

SDC problem

Stratix iv GT General Purpose I/O's

(CycloneV) Writing 128bits to FPGA at once using linux kernel module

simple pin to pin delay managing in Cyclone

Issues with Help content not displaying on left window pane

Nios2 console output

Megafunction plugin missing

Incremental Motor Encoder -- How Best to Count Transitions

Component TCL file in Qsys

Resource utilization is 0 when added qxp file as source file

Transfer data from HPS DDR3 to FPGA SDRAM and back using DMA

Featured Content

AGILEX5 - HPS-first - timeout waiting for RECONFIG_COMPLETED

10M04SCU324I7G - I/O timing

SDI pinning on Agilex 5

I350 igb driver failed with error -2

Request for the Product Lifecycle Status

Re: USB Blaster selection criteria

Solution: USB Blaster Driver for Windows 11 ARM

Re: MAX10 (Select Internal Configuration mode with ERAM )