http://www.alteraforum.com/forum/attachment.php?attachmentid=12449&stc=1
the signal ports IFCLK, SLRD,FLAGS,DATA and SLOE are all from FPGA to Peripheral, in other words, they are all output for FPGA. In the timequest, what can I do to constraint the SLOE ? The setup time and hold up time of SLOE to clock isn’t directly given. the signal ports IFCLK, SLRD,FLAGS,DATA and SLOE are all from FPGA to Peripheral, in other words, they are all output for FPGA. In the timequest, what can I do to constraint the SLOE ? The setup time and hold up time of SLOE to clock isn’t directly given.
