Cyclone II ESD Problem

[Altera_Forum]

Hi there, 

 We are experiencing very strange behavior of the FPGA (EP2C5T144C8) when conducting ESD tests according to IEC 61000-4-2. During the indirect discharge test, the FPGA freezes and all I/Os become low level. The buffers do not respond to any change. The implemented internal logic reset is not working also. When I drive the nCONFIG to low the reconfiguration is started and completed successfully (the nSTATUS is transitioning to low and than to high), but the buffers still do not respond and stay at low level. Only reset of the power supply is restarting the FPGA. I think it could be something with the internal hot socketing feature of the I/Os. Probably we have some issues with the PCB power and ground planes but I've never seen such a behavior of the FPGAs. Do you have any suggestions how to reset the IO buffers without interrupting the 3.3V PS or something that could prevent freezing of the I/O buffers?  Thanks. Victor

[Altera_Forum]

Since it requires a power cycle to come out of this condition, it sounds like you are getting it into a latchup condition. 

 I've never seen this particular issue, with the Cyclone II, but that doesn't meet it doesn't exist.  Have you tried to wiggle the IO's with jtag boundary scan? Also does the current draw of the part go up (for the IO banks) when it's stuck in this condition?   I've seen EDS testing destroy IO's, but that usually is destructive and non-recoverable.  Pete

[Altera_Forum]

Hi Pete, 

 After indirect arc test the FPGA seems ti get in latch-up. The 1.2V rail current is increased by 60mA. Only reset on the 1.2V rail removes this condition.  Thanks Victor

[Altera_Forum]

I imagine that the observed global latchup can be only triggered by pushing a supply line beyond rate voltage range. Sufficient bypassing and additional transient suppressors if necessary should help. 

 Where do you apply the ESD discharge?