Cyclone II , Fifo UART, Nios II

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Cyclone II , Fifo UART, Nios II

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Hello,

Maybe i have problems to setup this Fifoed Uart.

http://www.alterawiki.com/wiki/fifoed_avalon_uart

Could you please send me an example .qsys setup and an example code with the general Nios II (not second gen) processor?

I already setup a configuration with an example code and connected the Tx and Rx together, but when i sending a byte then i dont get any interrupt.

Thank you very much!

Best regards,

Mate

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