Hi All,I am using Cyclone III: EP3C40F780C6N FPGA. We are using this for capturing the Image from the sensor. As per the data sheet it should support up to 875 Mbps. I am able to get the valid Image data up to 300 Mbps. After that my image data is getting skipped or not getting valid data from the FPGA even if the sensor is throwing valid data. I have verified the eye opening in the FPGA receiver end and it is 110mV differential. All the timing Constraints for the PLL & input clocks were added Please help on this. Thanks in Advance.
Please give complete information about the design. What does it mean "data is getting skipped"?Timing constraints might be insufficient to get proper LVDS receiver phase at highest bit rates. Phase adjustment might be necessary.