Cyclone III PLL VCO Granularity

[Altera_Forum]

Hi all, 

 I would like to reconfig the PLL to different frequencies given by a string. I use a PIC for that and kind of a brute froce method. To calculate the error i need to know the PLL internal VCO frequency and there I have a question. What values are allowed there? I knwo that they have to be between 600 and 1300MHz but are there kind of steps between there? If I use the mega-wizard and want to achieve an output frequency of 119.7 (input 12MHz) he suggests an output divider of 5 which would be then 598.5 fvco. I can see in the details that it is actual 600MHz. Why is that. Why doesn't he choose 599 MHz. How big are the steps and are they the same in the whole range?  Thanks Oliver

[Altera_Forum]

Regarding 599 mhz, I believe you answered your own question, but I will just state it another way. If the VCO freq is outside 600-1300mhz, then mega wizard will adjust the settings so the VCO is within its operation range. So if you have a 12Mhz input, the minimum frequency multiplier that can be used is 50 otherwise you would have no chance to hit 600mhz vco requirement. Then PLL can divide the VCO by k. 

 f= (12*(m/n))/k  You can use the mega wizard to recommend settings, and then dump the values to a ROM file in the wizard. The ROM files have parameter settings which you can use to reconfig the PLL.  I believe m & n are 8 bits and k is 16 bits.

[Altera_Forum]

Ok, I found out by myself. First, my example was veeery poor because I didn't recognise that I choose one which has an operating frequency outside the specs. What I meant did happen inside too. It's actually very simple and I just didnt't think things trough. If I have an input frequency of 12 MHz and we assume n to be 1, the one frequency at the PFD (fref) is also 12 MHz. So he of course chooses m the way that fvco/m is fref so the PLL is locked (also assuming post-scale counter to be 1). I first calculated the other way around. Given an output frequency of i.e. 23.158 MHz and an output divisor of 30 the fvco should be 694.74MHz. He now searches to nearest integer which has no remainder after dividing with 12 and thats m and thats also what I first did not recognise. Here it is m = 58 and therefore fvco = 696MHz. With a known fvco I can now calculate the real output frequency fout = fvco/30 = 23.2MHz. 

 Well, what I actually want to do is to reengineer the algorithm used by the mega-wizard to determine the different values. Kind of a brute-force approach already works. But I don't know if it's fast enough for a microcontroller implementation... If anybody has another idea I would be very glad to hear it.  And I think m, n and k are all 9 bits as they can have values between 1 and 512 if I'm right.

[Altera_Forum]

if your output clock has a duty cycle of 50% M and N should also range 1:512, see page 9 note 1: 

 http://www.altera.com/literature/hb/cyc3/cyc3_ciii51006.pdf