the function of every IO Pin of (EP2C5T144)FPGA

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the function of every IO Pin of (EP2C5T144)FPGA

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I am a beginer. In the pin setting of quartus, I see the pins of EP2C2T144 have a lot of second or third function. I didn't have the datasheet about the detail function of every pin. (for example PIN_17 CLK0/LVDScLK0p/input , PIN_24 LVDS4p/DPCLK1/DQS1L/CQ1L# ) . For example, in a project, I creat a ALTPLL and the input pin must be CLK0~CLK3 or else common pins?? I knew the OSC should be connected to the CLK0. Should a signal which has the 65MHz Fre. have to connect to the CLK0~3 or else commom pin?? How to deal with it??

regards

cheng_bei

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