Cyclone III and SDR SDRAM

[Altera_Forum]

Hi, 

I want to connect SDR SDRAM to Cyclone III, but I'm a little confused about voltage levels(LVTLL 3.3V). I've read http://www.altera.com/literature/an/an447.pdf but I'm not sure I understand it correctly. Have somebody successful used SDRAM without any termination resistors? I've checked IBIS model like they showed on page 13 and the result is that I must use resitors. But simulation results seems ok for me without them. What is the maximum current that C III receiver can take? Can it exceed 30 mA? I think that only voltage overshot can damage the pin? How should I use termination resistors on bidirectional lines? Place resistor on both sides of transmition lines?  Sorry for my poor English.

[Altera_Forum]

Look at the table on Page 3 of an447.pdf the SDRAM is your 'driver' in this case, reference the datasheet for your SDRAM to obtain it's operational voltage on it's interface pins to determine whether you require termination resistors or clamping diodes activated on the Cyclone III. 

 Use Table 3 on Page 10 with the voltages you assumed on Table 1 to determine the the value of the current flowing into a receiving pin on the cyclone with no termination, and if termination resistors are required.  Your still not done though, remember you have to do this same process with your 'driver' if it is using bi-directional interface pins, using the specifications in the datasheet for your SDRAM.  Look at schematics for the Cyclone III Nios Embedded Evaluation Kit (download zip from Altera's site)  From what I understood on the Cyclone III NEEK schematic you should place only one set of termination resistors in the centre of the transmission lines, also by the look of the PCB layout all lines must be equal in length.  I'm 80% sure thats the angle of attack required, someone shoot me down if i'm talking sloblocks

[Altera_Forum]

3.3V SDR SDRAM can be operated with Cyclone III without problems, I just ported a respective Cyclone I design to Cyclone III. Regarding possible overshoots, the best solution is to prevent any overshoots by a suitable design. If the RAM is placed close to the FPGA, no particular means are most likely required. If external logic is driving 3.3V to the FPGA over longer distances than 2", it may need series termination (e.g. 50 ohms), if not yet included in the driver. This way, you are able to achieve a good signal quality with usual PCB wiring and don't need any PCI clamp diodes with on-board generated signals.

[Altera_Forum]

FvM, what did use for the memory controller IP? The included ones in quartus do not support SDR SDRAM on Cyclone 3 for reasons I do not fathom. Can I just configure it as though it were a cyclone1 and drop them MF into a cyclone 3? 

 Thanks-  Tim

[Altera_Forum]

Hi, 

 I found that 3C25 standard nios II example really got problem. when i run a simple hello world example from NIOS II template, it has the error where verify address failed at the address pointing to the sdram. anyone has the same issue?  caridee