Programmable Devices
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Stratix III power consumption

Altera_Forum
Honored Contributor II
‎04-22-2010 01:45 PM
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Prior to configuration, the power consumption of my Stratix III (EP3SL340H1152I4) seems abnormally high. The chip is literally too hot to touch. The Stratix is configured by a uProc via FPP. At first I was thinking maybe the CONFIG_n line is constantly being strobed forcing the chip to repeatedly initialize itself but the line is always high. Just to verify STATUSn is also always high. The DCLK line is also a constant high. All the VCC's are connected properly (Vcc_aux = 2.5V, VCCL = 0.9V, VCC = 1.1V, VCC_CLK = 2.5V, VCCA = 2.5V, VCCD = 1.1V, VCC_PGM = 3.3V, VCC_IO = 3.3V). 

 

Does anyone have any ideas what could be causing such a large heat dissipation prior to configuration?
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Altera_Forum
Honored Contributor II
‎04-22-2010 08:36 PM
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1 - Does the power consumption drop after the FPGA is configured? 

2 - How hot is the part (using a thermal gun, imager, or thermocouple). 

3 - Are any of your power supplies showing significant current draw? 

 

Jake
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