Cyclone III: can't achieve specified port rate

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Cyclone III: can't achieve specified port rate

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Hello,

I have problems to meet timing requirements, getting "minimum pulse width"-violations with "port rate"-type.

Design consists of clock input (50MHz, pin_t9), PLL and clock output(100MHz, pin_l1). Device is EP3C25U256C8. Current strength @8mA, slew rate 2.

Timequest reports "minimum pulse width"-violations at the clock output with -3.481 slack.

If I understand it correctly, the output toggle rate is specified up to 200MHz with this settings. Any suggestions what the problem is?

Best regards

Jaroslav

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